Extraction & DFM

Just Listing down every thing without proper formatting (just because of lack of time)... Will update this page later some time.


Chapter 1: Parasitic Extraction Introduction

• 1.1a Metal Layer Stack (Metallization Option)
• 1.1b Metal layer Stack (Nomenclature)

Chapter 2: Parasitic Interconnect Corner (RC Corner)

• 2.1a Basics Of Capacitance and Resistance (From VLSI design Point of view)
• 2.1b Interconnect Corners (Cmax, Cmin, RCmax, RCmin)
• 2.2 Interconnect Delay Models
• 2.3 How to Read SPEF
• 2.4 Difference between Parasitic Data Format

Chapter 3: Manufacturing Effects and Their Modeling

• 3.1 Manufacturing Effects Introduction
• 3.2a Effect of Etching Process (Variation in width of layer)
• 3.2b Effect of Etching Process (Variation in Thickness Of layer)
• 3.3a CMP (Chemical Mechanical Planarization)
• 3.3b Importance of CMP process
• 3.3c CMP effects (Dishing and Erosion)
• 3.4 Lithography
• 3.5a Metal Width Variation (Type1 and Type2)
• 3.5b Metal Width Variation (Type3)
• 3.5c Metal Width Variation (Type4 and Type5)
• 3.5d Metal Width Variation (Type6)
• 3.5e Metal Width Variation (Type7)
• 3.5f Metal Width Variation (Type8)
• 3.5g Metal Width Variation (Summary)
• 3.6 Metal Thickness Variation (Type3)

Chapter 4: Dielectric layer

• 4.1 Conformal Dielectric
• 4.2 Modelling of Dielectric Layer in Technology File

Chapter 5: Process Variation

Chapter 6: Other topics (Will categorize later)

• 6.1 Antenna Effect
• 6.2 Parasitic Extraction (ppt) - (lecture Notes by CK Cheng)
• 6.3 Coupled And Decoupled Capacitance Extraction