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Friday, December 24, 2021

TCL Practice Task S2_1 (Scripting Language)


While working on industry grade EDA tools, it is important to understand the working of commands. However most important are switches used along with the commands. These switches are designed in such a way that it acquire sufficient information from the end user (user that is using the command). As a end user you can control the command also or say you can instruct the program to execute the command in a specific manner.
For Example There is a program that can extract 10 different informations from a file but may be as a user you don't want all those information at the same time. If you want that program should give you only 5 informations, than obviously you have instruct the program. A good program is the program which give flexiblity to the end user to instruct the program (even though that's your program but end user think that they are controling the program :) )

Both the above mentioned things can be easily done with the help of switches. There are 2 type of switches.
  • Optional Switch
    • It's user dependent
    • If user define/uses these switches while runing/executing the program, respective program of task is going to perform else no need to perform task
  • Mandatory Switch
    • User has to provide the value of this else program is not going to work - or program will give you an error
So, I am back here to help you in developing that skill along with automation which will create a background of understanding that how industry tools works.

This is the first program of Second series of TCL Scripting language. If you have done all 4 task of Series 1, It's good but in case you missed that - Complete them first (even before starting this program).  TCL Practice Task 1TCL Practice Task 2, TCL Practice Task 3TCL Practice Task 4,
  


PART 1 of S2_1

Step 1: Create a input file as mentioned below.    

##################################################################


Startpoint: DFFPOSX1_3 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: reg-to-out
Path Type: max

Delay      Time          Description
---------------------------------------------------------------
0.00          0.00          clock clk (rise edge)
1.23          1.23          clock network delay (prop)
0.16          1.39  ^     DFFPOSX1_3/CLK (DFFPOSX1)
0.27          1.66  v     DFFPOSX1_3/Q (DFFPOSX1)
0.08          1.74  v     BUFX2_1/Y (BUFX2)
0.13          1.87  v     out1 (out)
                1.87 data arrival time

1.00      1.00      clock clk (rise edge)
1.43      2.43      clock network delay (prop)
-0.25     2.18      Uncertainty
0.54      2.72      clock reconvergence pessimism
-2.50     0.22      output external delay
            0.22      data required time
---------------------------------------------------------------
           0.22      data required time
            -1.87      data arrival time
---------------------------------------------------------------
    slack     -1.65      (VIOLATED)

Startpoint: DFFPOSX1_3 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: reg-to-out
Path Type: max

Delay      Time      Description
---------------------------------------------------------------
0.00          0.00      clock clk (rise edge)
1.23         1.23        clock network delay (prop)
0.16         1.39  ^     DFFPOSX1_3/CLK (DFFPOSX1)
0.27         1.66  v     DFFPOSX1_3/Q (DFFPOSX1)
0.08         1.74  v    BUFX2_1/Y (BUFX2)
0.13         1.87  v    out1 (out)
                1.87    data arrival time

1.00          1.00      clock clk (rise edge)
1.43          2.43      clock network delay (prop)
-0.25         2.18     Uncertainty
0.54          2.72     clock reconvergence pessimism
-2.50         0.22     output external delay
                 0.22      data required time
---------------------------------------------------------------
                0.22    data required time
                -1.87   data arrival time
---------------------------------------------------------------
slack     -1.43      (VIOLATED)

##################################################################

Step 2 : You have to create a command line script cum procedure, which will take the Step 1 as a input file with a switch; and other user defined switch which will output the certain values. It should be like “report_parameter.tcl -input report.txt -dat -drt -slack -cppr -skew -path_group” 

(Note: I am not specifying the switch name - you can choose yourself. Use a Switch --help which user can use to find out all the switches). 

Step 3 : Output should be dumped into a csv file (Comma separated value file). This is very common file in Industry and whenever you are going to open this file using excel or libreoffice (in linux). Please find the csv file snapshot.

Parameters, Report 
slack,-1.65
ext_delay,3.00
uncertainty,0.25
cppr,0.54
data path delay,1.87
Skew,0.20




PART 2 of S2_1


Repeat all the steps with the help of attached file - which is bigger in size and as per Industry requirement.

STEP 1 Full report_file

I am sure this article will help you to prepare for TCL scripting. I have few more such programs which I will try to capture later sometime.


-By Rajat Bansal
(Btech-EC:- 2019 Passout)
https://www.linkedin.com/in/rajat-bansal-3400009b/


-Supervised By Puneet Mittal
(Founder & Director)
(VLSI Expert Private Limited)

Wednesday, December 15, 2021

LTSPICE Based Self-Practice Questions

We have seen a lot of students facing problems while working on several basic concepts. To understand those concepts, it's very much required to do some testing and simulation and assess yourself how much you are able to grasp the concepts.

Below are few questions which you can try over LTSPICE yourself and understand the different design concpets. It will help you in VLSI Industry, the real simulation based concepts.

Please try to solve these questions yourself.

Q1) Design the circuit which is provided with the input Vin as shown in left figure and output is obtained as Vout as shown in the right figure


Q2) For the circuit shown below which one is better Explain and support your answer with LTSPICE Simulation


Q3) For the given netlist generate the schematic on LTSPICE. What kind of analysis is being done here

VIN 1 7 AC 0V
IST 0 10 AC 1MA
VX   10 6 DC 0V
VDD 8 0   15V
RS    1  2    250
C1    2  3    IUF
R1    8  3    1.4MEG
R2    3  0   1MEG
RD    8  4     15K
RS1   5  9     100
RS2   9  0      15K
CS     9  0       20UF
C2    4   6       0.1UF
R3    6   7      15K
R4    7   0      5K
M1  4   3    5   5 MQ
.MODEL MQ NMOS (VTO=1 KP =6.5E-3  CBD=5PF
+RG =0 RDS =1MEG CGSO=1PF CGDO=1PF CGBO=1PF)
.AC DEC 10 10HZ 10MEGHZ
.PROBE
.END





Q4) Design a circuit for the given input and output waveform given below and after designing it draw the schematic on LTSPICE and verify that the circuit indeed generate the waveform given in here


Q5) Explain what is wrong in the Model statements given below

1)
.MODEL MQ NMOS (VTO=1 KP =6.5E-3 CBD=5PF
+RG =0 RDS =1MEG CGSO=1PF CGDO=1PF CGBO=1PF)
R1    4  3  5  5   MQ

2)
.MODEL QNP NPN (BF =50 RB=70 RC =40 TF =0.1NS TR =10NS VJC=0.85)
M1    4  3  2  QNP

3)
.MODEL DIODE D (RS =40 TT =0.1NS)
Q1    4  5  DIODE

Q6) For the Circuit shown below:
  1. Shown the voltage across the Resistor R3 and R4
  2. Find the Voltage VA ,VB,VC
  3. Also Justify the value using LTSPICE Simulation


Q7) For the circuit shown below write the netlist also you need to include the model used for MOSFET and Resistor


-Prepared By Niti Gupta
(Director of eLearning and university Program)
(VLSI Expert Private Limited)

-Supervised By Puneet Mittal
(Founder & Director)
(VLSI Expert Private Limited)

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