Latch based Timing Analysis - Part 1

This series we are starting for Latch based Timing Analysis. In case of Latch, there are lot of basic concepts which are similar to Flipflop based Timing but still we get confuse a lot of time, I am going to try my best to clarify that.

Let's first try to understand Flipflop Vs Latch when we are doing Timing analysis. You will see everything is almost same.

In the above circuit you can see that everything is same, only difference - LATCH is placed in place of FLIPFLOP. Apart of this - understanding of Launch Latch and Capture Latch is same.

• Launch Latch - The Latch which is going to launch the data.
• Capture Latch - The Latch which is going to capture the data.

Below comparison also give you understanding between different other terminologies. Like Capture clock path, Launch clock path, Arrival data path, Required path.

Apart of this - remember - all the Timing Terminologies are same in case of Latch. Only difference is the way you are going to apply these concepts. Now, question come why? - because there is a difference in the functionality of the Flipflop and Latch.

Latch is level Triggered and Flipflop is Edge Triggered - this is something everyone know. More specifically - A latch is a level-sensitive storage cell that is transparent to signals passing from the D input to output Q when it is enabled. Latch holds the values of D on Q as Latch become disable. Depending on the polarity of the enable input, Latches are of Positive or Negative level. Flip-flop is an edge-triggered device that changes state at Q as per D on the rising or falling edge of an enable signal. Flipflop holds the values of D until the next respective (rising or falling) edge of the enable signal.

But when I have asked couple of people what will happen in case of Latch at the edges - so either they become confuse or don't have clear understanding. Try to understand this from the following waveform (Launch and Capture clock of latch means - clock which is enable Launch and Capture Latch).

Lets understand this …

Eligibility of Launch Latch (which is Positive level latch) to launch data started the moment there is a rising edge (enable signal making transaction from Negative level to Positive level). It can launch the data continuously (means passing the data from D to Q or say created a continuous path between D and Q) till latch is disabled. This disable activity started at falling edge (the moment enable signal making transaction from Positive Level to Negative level). Now, try to understand the "First edge used for Launch" and "Last edge used for Launch" in the above waveform diagram.

Let's take the example of Data launch at the first edge of the Launch waveform -

1. Data A (red data in above fig) - Delay between the Launch and Capture Latch is very less, then data can be capture at the first positive Level itself at the Capture waveform (as showing in the figure)
• Remember - this is Latch and Latch is transparent at level. In case of Flipflop - data capture only at the edges.
2. Data B (Orange data in above fig) - Delay is significant. Data can reach at D pin of Capture Latch when Latch was disabled. So now, it can only be capture next time when capture Latch is going to enable. Since Data is already present (before the Capture Latch enable), eligibility of capture Latch (which is Positive level latch) to capture data started the moment there is a rising edge (enable signal making transaction from Negative level to Positive level).
• Remember - If you compare this scenario you will find no difference between Latch and Flipflop. Because both are launching the Data at Rising clock edge and both will capture the data at Rising clock edge. :)
3. Data C (green data in the above fig) - Delay is more. It's reaching at D pin of Capture Latch when latch become enable already (second time). Since Latch is already enable, data can easily capture by Latch and passes to Q pin at the same time.
• Remember - If we want that data should be captured by latch at this level only (when capture latch enable second time), then we have to make sure that data should reach at D pin before the Latch disable - means before Falling edge of clock :).
• Remember - If this is the case of Flipflop - then either we have to reduce the delay or we have to make this path as multi-cycle path. But In Latch, still no need of multicycle concept. :)

Now, try to understand the "First edge used for Capture" and "Last edge used for Capture" concept in the above waveform diagram.

If you can understand above diagram, I can say that Latch can start sampling data from the rising edge (or falling edge) itself and continue sampling till the respective falling edge (or rising edge). And Flipflop can only sample the data "at" Rising edge or Negative edge. Both holds the data when they are disable (Latch disable at level and Flipflop disable just after triggering level).

Generally designers prefer flip flops over latches because of this edge-triggered property, which makes their life easy to do analysis and interpretation the design. Latch based design give you a lot of flexibility but remember nothing comes free. You have to pay your TIME and ATTENTION for that. :)

E.g -

1. Latch-based designs are preferred in case of clock frequency in GHz (in high-speed designs). In flip-flop-based high-speed designs, maintaining clock skew is a problem, but latches ease this problem.
2. In the design, slowest path decide the frequency of the design - means at which frequency design can work correctly.
3. Latch based design are more susceptible from process variation.

Now, Lets try to understand below diagram. I am sure, now it's very simple to understand. Different Data are launched between First edge and Last edge used for Launching purpose of X1 level from Launch Latch. As per our expectation, these data should be captured by X2 level at capture Latch (Between first and Last edge used for capturing purpose). If any Data don't reach by the time of Falling edge of Level X2 at capture Latch, we will consider that as not Captured. Now, try to correlate this uncaptured data with Violation of data (what ever we have discussed in Setup and Hold time/violation of Flipflop).

In the next article, we will discuss the Setup/Hold and Delay of Latch. Stay Tuned :)

How To Read SDF (Standard Delay Format) - Part5

In the last few articles (PART 1, PART 2 and PART 3), we have discussed the following things

• SDF different sections and different construct - In PART 2
• Cell Section details - In PART 3
• Delay Details in SDF - In PART 4

Now. it's the time to discuss about the SDF using an example.

Lets discuss the below circuit.

As a part of SDF, if you remember, we have discussed in PART 2 - that there is a HEADER section, Then CELL Section. In our circuit, there are 5 instance of Cells - r1, r2, r3, u1 & u2. These cells are mapped with Library as (This information you can get from .lib or from .v file)

r1, r2 and r3 -> DFF_X1
u1 -> BUF_X1
u2 -> AND2_X1

Header Section - marked as RED Color
CELL Section where we are talking about interconnect Delays - marked as GREEN color
CELL Section with respect to Flipflops - marked as BLUE color
CELL Section with respect to Buffer - marked as BLACK color
CELL Section with respect to AND gate - marked as LIGHT GREEN color.

And that's all the construct.

(DELAYFILE
  (SDFVERSION "OVI 2.1")
  (DESIGN "vlsiexpert")
  (DATE "Thu Dec 12 20:33:26 2019")
  (VENDOR "vlsiexpert")
  (PROGRAM "customized")
  (VERSION "01")
  (DIVIDER /)
  (VOLTAGE 2.25:2.25:2.25)
  (PROCESS "1.000:1.000:1.000")
  (TEMPERATURE 125.00:125.00:125.00)
  (TIMESCALE 1ns)

  (CELL
   (CELLTYPE "vlsiexpert")
   (INSTANCE)
   (DELAY
    (ABSOLUTE
// Offset in1 vs in2, rise vs fall arrivals so results are deterministic.
     (INTERCONNECT in1 r1/D (0.011:0.011:0.011) (0.01:0.01:0.01))
     (INTERCONNECT in2 r2/D (0.021:0.021:0.021) (0.02:0.02:0.02))
     (INTERCONNECT clk1 r1/CK (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT clk2 r2/CK (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT clk3 r3/CK (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT r1/Q u2/A1 (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT r2/Q u1/A (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT u1/Z u2/A2 (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT u2/ZN r3/D (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT r3/Q out (0.0:0.0:0.0) (0.0:0.0:0.0))
    )
   )
 )

 (CELL
  (CELLTYPE "DFF_X1")
  (INSTANCE r1)
  (DELAY
   (ABSOLUTE
    (IOPATH CK Q (1:1:1) (1.1:1.1:1.1))
   )
  )
  (TIMINGCHECK
   (SETUP D (posedge CK) (.5:.5:.5))
   (HOLD D (posedge CK) (.1:.1:.1))
   (PERIOD (posedge CK) (1.0:2.0:3.0))
  )
 )

 (CELL
  (CELLTYPE "DFF_X1")
  (INSTANCE r2)
  (DELAY
   (ABSOLUTE
    (IOPATH CK Q (1:1:1) (1.1:1.1:1.1))
   )
  )
  (TIMINGCHECK
   (SETUP D (posedge CK) (.5:.5:.5))
   (HOLD D (posedge CK) (.1:.1:.1))
   (PERIOD (posedge CK) (1.0:2.0:3.0))
  )
 )

 (CELL
  (CELLTYPE "DFF_X1")
  (INSTANCE r3)
  (DELAY
   (ABSOLUTE
    (IOPATH CK Q (1:1:1) (1.1:1.1:1.1))
   )
  )
  (TIMINGCHECK
   (SETUP D (posedge CK) (.5:.5:.5))
   (HOLD D (posedge CK) (.1:.1:.1))
   (PERIOD (posedge CK) (1.0:2.0:3.0))
  )
 )

 (CELL
  (CELLTYPE "BUF_X1")
  (INSTANCE u1)
  (DELAY
   (ABSOLUTE
    (IOPATH A Z (1:1:1) (1.1:1.1:1.1))
   )
  )
 )

 (CELL
  (CELLTYPE "AND2_X1")
  (INSTANCE u2)
  (DELAY
   (ABSOLUTE
    (IOPATH A1 ZN (1:1:1) (1.1:1.1:1.1))
    (IOPATH A2 ZN (1:1:1) (1.1:1.1:1.1))
   )
  )
 )

)

Note:

• In the Interconnect Delay, SDF has delays of all 10 wires/interconnects.
• Input port to Reg input D pin (in1 to r1/D , in2 to r2/D)
• Clock_source to Clock_input pin of Register (clk1 to r1/CK, clk2 to r2/CK, clk3 to r3/CK)
• Reg output Q pin to Output port (r3/Q to out)
• All internal combinational nets
• For all flipflop we have all required info which we need from .Lib
• Clock to Q delay
• Setup and Hold constraint
• Positive Edge or Negative Edge triggered Flipflop
• Clock Time period information
• For all other logic cells, we have following information
• Cell Rising and Falling delay
• Cell - Min, Max and Typical Delay
• Input pin - output pin specific delay (also know as ARC delay - like in case of AND - a->y and b-y)

How To Read SDF (Standard Delay Format) - Part4

In the last few articles (PART 1, PART 2 and PART 3), we have discussed the following things

• What is SDF and what information it contain?
• Construct of SDF (2 Section – Header and CELL)
• Header Section contain general information about the Tool which is used to create/generate the SDF and the Design related information (like Design name, Process, Voltage, Temperature of the design for which SDF is generated).
• Cell Section can be multiple in the SDF file. These CELL section can represent to a specific Primitive cell (standard Cell) or a region of the design (Blocks) or any instance in a hierarchy.
• Cell section has 3 different sub-section – CELLTYPE , INSTANCE, Timing specification section.
• Timing specification section contain actual timing data associated with that cell. There are four types of timing specifications that are identified by the DELAY, TIMINGCHECK, TIMINGENV, and LABEL keywords.
• DELAY: Specify the delay related information for back-annotation.
• TIMINGCHECK: Specify Timing checks limit data for back-annotation
• TIMINGENV: Specify timing environment data and constraint data for forward-annotation.
• LABEL: Set the values of timing model variables upon that delays and timing constraint values depend

In this Article, we will discuss more details about the DELAY construct. This is the most important part of the SDF. It’s a Standard Delay format – so it’s important to have a separate Article only for Delay.

Delay values are defined in SDF in the form of list. This list can have 1,2,3,6 or 12 pairs. These pairs are corresponds to the transition of the signal at the output port. The sequence of those transition is fixed and described in the following table.

Note:

• If only 1 pair is present in the delay list then it’s same for all 12 transition.
• There are chances that in SDF, any pair has NULL value. It is consider as placeholder for that particular transition. Means the stage where SDF is created, the delay info corresponding to that transition is not available and later it can be filled.

Example 1: (IOPATH i3 o1 () () (2:4:5) (4:5:6) (2:4:5) (4:5:6))

In the above example, there is no delay value present for 0->1 and 1->0 transition.

Type of Delay:

There are 2 types of Delay based on how it will be annotated into the design.

Incremental Delay: If any delay value is defined under this category it means it will add SDF value into the Delay present in the design (at the time you are trying to annotate SDF delay).

Absolute Delay: If any delay value is defined under this category it means it will replace the Delay present in the design (at the time you are trying to annotate SDF delay).

Category of Delay in SDF:

Delay in the SDF can be any of the following category.

1) Input-output path Delay:

• Represent the delays on a legal path from an input/bidirectional port to an output/bidirectional port of a device. Each delay value shall be associated with a unique input_port - output_port pair.
• Input or a bidirectional port can have an edge identifier.
• No edge Identifier can be present in case of output or a bidirectional port.
• Representation of Delay values are in the same fashion as explained in above.
• Construct used in SDF : IOPATH

Note:

• For in1, positive edge identifier is specified.
• These Delay are absolute (ABSOLUTE) in nature. Means it’s going to replace any delay specified in Timing models for these paths under specified transitions.
• For in3, delay values are NULL for first 2 transition (0->1 and 1->0). It means for these transition, Delay values are unchanged (it will remain as-it-is as in the timing models).

2) Conditional path delays:

Now if you want to apply a particular condition before applying a particular path delay, we can use this method. The conditional path delay shall specify conditional (state-dependent) input-to-output path delays.
There are 2 ways to apply the conditions

• If a Particular Condition met, then apply the Delay value
• The annotator must locate in the timing model a path delay with conditions matching those specified in the SDF file. Other path delays between the same ports but with different conditions shall not receive the data.
• The expression shall evaluate to a logical signal, rather than a boolean. The analysis tool shall treat a logical zero as FALSE and any other logical value (1, X, or Z) as TRUE. A particular conditional path delay in the timing model shall be used only if the condition is TRUE.
• Use the SDF Construct : COND
• If a Particular Condition doesn’t met, then apply the Delay value
• The delay values specified in SDF shall be used if none of the conditions specified for the path in the model are TRUE but a signal must still be propagated over the path.
• Use the SDF construct: CONDELSE

3) Port Delay:

• Port delay specify the interconnect delay (actual or estimated) that are modelled as delay at input port.
• Use the SDF Construct: PORT

Note: Above delay is applied same for net between “y” and “c.r1.a” and “c.r2.a”.

4) Interconnect Delay

• The interconnect delay shall specify the propagation delay across a net connecting a driving module port (the source) to a driven module port (the load).
• Either or both ports can be bidirectional. Both source and load ports for the delay path shall be specified.
• Use the SDF Construct: INTERCONNECT

5) Net Delay:

• The net delays shall specify the propagation delays from all sources to all loads of a net.
• Neither start nor end points for the delay path are specified, and the delays from all the source ports to all the destination ports will have the same value.
• Use the SDF Construct: NETDELAY

There are other SDF construct also but I am not discussing them here. The reason being – it will increase the length of the Article & looks to me that’s not required right now.;) For the detail info, you can refer the “IEEE standard for Standard Delay format for electronic design format”. Most of my content also have same reference.

Apart of this – Most important thing is SDF constructs are originally targeted for annotation to tools using the Verilog language, so many SDF constructs are analogous to those in Verilog specify blocks. Those already familiar with the Verilog specify block will find many of the SDF constructs familiar. So it’s very easy for those who are champ in Verilog. 

In the Next Article, we will take a circuit and respective SDF, to give you an idea - how to read SDF with respect to a circuit.

STA Tool Command - report_timing -max_paths_count (OpenSTA -group_count) : Part 2

In the previous part (STA Tool Command - report_timing -max_paths_count (OpenSTA -group_count) : Part 1) we have discussed about the switch -group_count for 1 circuit. As per our initial understanding -group_count is correspond to "The number of paths to report in each path group". But when we have checked practically, we have noticed different behavior (Summarized in the below table).

Clock Group	group_count	Total No. Of Reports
1	1	1
1	2	2
1	3	3
1	4	3
1	5	3
1	...	3
2	1	2
2	2	3
2	3	3
2	4	3
2	5	3
2	...	3

I have asked all of you to guess the reason of that but I am not sure how many of you were able to do it. :) Maybe, some of you have created a relationship between Total no of Reports Vs Total Number of Flipflop present in the circuit. :) Let's see if it's true for another circuit also. :)

CASE1:
create_clock -name clk -period 10 {clk1 clk2 clk3 clk4}
set_input_delay -clock clk 0 {in1 in2 in3}

report_checks -format summary -path_group clk -group_count 1

Startpoint           Endpoint        Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1) r3/D (DFF_X1) 9.22

I have made only one clock group therefore when group_count is 1 only one path is reported. Lets increase group_count and see what will happen.

report_checks -format summary -path_group clk -group_count 2

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.22
r2/Q (DFF_X1)           r4/D (DFF_X1)           9.24

Here group_count is 2 that’s why two paths are reported.

For group_count = 3

report_checks -format summary -path_group clk -group_count 3

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.22
r2/Q (DFF_X1)           r4/ (DFF_X1)           9.24
in1 (input)                 r1/D (DFF_X1)           9.85

Here group_count is 3 that’s why three paths are reported.

report_checks -format summary -path_group clk -group_count 4

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.22
r2/Q (DFF_X1)           r4/D (DFF_X1)           9.24
in1 (input)                 r1/D (DFF_X1)           9.85
in2 (input)                 r2/D (DFF_X1)           9.85

Four reports since group_count is 4

report_checks -format summary -path_group clk -group_count 5

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.22
r2/Q (DFF_X1)           r4/D (DFF_X1)           9.24
in1 (input)                r1/D (DFF_X1)           9.85
in2 (input)                r2/D (DFF_X1)           9.85

The question arises here, that group_count is 5 then why only four paths are reported?

Now, try to compare previous example (in the previous part of this article) and this example. In previous example, with 1 clock group, maximum paths were reported 3 even though we have increases group_count more then 3. In this example, maximum paths reported are 4 even if we increase group_count more then 4.

Hint is – check number of Flipflop in both circuit and now, I am sure that you can say that it's related to total number of Flipflop. :) But remember - this is just HINT - Answer is something else.

CASE2:
create_clock -name ck1 -period 10 {clk1 clk2}
create_clock -name ck2 -period 10 {clk3 clk4}
set_input_delay -clock ck1 0 {in1 in2}
set_input_delay -clock ck2 0 {in3}

report_checks -format summary -path_group {ck1 ck2} -group_count 1

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
in1 (input)                 r1/D (DFF_X1)           9.85
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.22

report_checks -format short -path_group {ck1 ck2} -group_count 1

Startpoint: in1 (input port clocked by ck1)
Endpoint: r1 (rising edge-triggered flip-flop clocked by ck1)
Path Group: ck1
Path Type: max

Startpoint: r2 (rising edge-triggered flip-flop clocked by ck1)
Endpoint: r3 (rising edge-triggered flip-flop clocked by ck2)
Path Group: ck2
Path Type: max

Here I have made two clock groups that’s why one path is reported from each clock group when group_count is 1

For group count = 2

report_checks -format summary -path_group {ck1 ck2} -group_count 2

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
in1 (input)                 r1/D (DFF_X1)           9.85
in2 (input)                 r2/D (DFF_X1)           9.85
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.22
r2/Q (DFF_X1)           r4/D (DFF_X1)           9.24

report_checks -format short -path_group {ck1 ck2} -group_count 2

Startpoint: in1 (input port clocked by ck1)
Endpoint: r1 (rising edge-triggered flip-flop clocked by ck1)
Path Group: ck1
Path Type: max

Startpoint: in2 (input port clocked by ck1)
Endpoint: r2 (rising edge-triggered flip-flop clocked by ck1)
Path Group: ck1
Path Type: max

Startpoint: r2 (rising edge-triggered flip-flop clocked by ck1)
Endpoint: r3 (rising edge-triggered flip-flop clocked by ck2)
Path Group: ck2
Path Type: max

Startpoint: r2 (rising edge-triggered flip-flop clocked by ck1)
Endpoint: r4 (rising edge-triggered flip-flop clocked by ck2)
Path Group: ck2
Path Type: max

group_count is 2 here, therefore two paths from each clock is reported.

When group_count = 3

report_checks -format summary -path_group {ck1 ck2} -group_count 3

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
in1 (input)                 r1/D (DFF_X1)           9.85
in2 (input)                 r2/D (DFF_X1)           9.85
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.22
r2/Q (DFF_X1)           r4/D (DFF_X1)           9.24

Now again something happens😊. Here group_count is 3, but path reported are only four why?

Now, lets try to understand this with the help of grouping of clock in different way.
In the last case, clk1 - clk2 & clk3 - clk4 were grouped together but in below case clk1 – clk3 & clk2 - clk4 group together. And see the difference and I am sure you can solve this puzzle.

CASE3:
create_clock -name ck1 -period 10 {clk1 clk3}
create_clock -name ck2 -period 10 {clk2 clk4}
set_input_delay -clock ck1 0 {in1 in3}
set_input_delay -clock ck2 0 {in2}

report_checks -format summary -path_group {ck1 ck2} -group_count 1

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.22
r2/Q (DFF_X1)           r4/D (DFF_X1)           9.24

report_checks -format short -path_group {ck1 ck2} -group_count 1

Startpoint: r2 (rising edge-triggered flip-flop clocked by ck2)
Endpoint: r3 (rising edge-triggered flip-flop clocked by ck1)
Path Group: ck1
Path Type: max

Startpoint: r2 (rising edge-triggered flip-flop clocked by ck2)
Endpoint: r4 (rising edge-triggered flip-flop clocked by ck2)
Path Group: ck2
Path Type: max

In case 3 also I have made two clock groups but the clocks grouped together are different. The results which you will observe here are same with respect to number of reports.

Now, lets see what will happen if we will increase group_count.

report_checks -format summary -path_group {ck1 ck2} -group_count 2

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)          r3/D (DFF_X1)           9.22
in1 (input)                 r1/D (DFF_X1)           9.85
r2/Q (DFF_X1)          r4/D (DFF_X1)           9.24
in2 (input)                 r2/D (DFF_X1)           9.85

report_checks -format short -path_group {ck1 ck2} -group_count 2

Startpoint: r2 (rising edge-triggered flip-flop clocked by ck2)
Endpoint: r3 (rising edge-triggered flip-flop clocked by ck1)
Path Group: ck1
Path Type: max

Startpoint: in1 (input port clocked by ck1)
Endpoint: r1 (rising edge-triggered flip-flop clocked by ck1)
Path Group: ck1
Path Type: max

Startpoint: r2 (rising edge-triggered flip-flop clocked by ck2)
Endpoint: r4 (rising edge-triggered flip-flop clocked by ck2)
Path Group: ck2
Path Type: max

Startpoint: in2 (input port clocked by ck2)
Endpoint: r2 (rising edge-triggered flip-flop clocked by ck2)
Path Group: ck2
Path Type: max

For group_count = 3

report_checks -format summary -path_group {ck1 ck2} -group_count 3

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)          r3/D (DFF_X1)          9.22
in1 (input)                 r1/D (DFF_X1)           9.85
r2/Q (DFF_X1)           r4/D (DFF_X1)           9.24
in2 (input)                 r2/D (DFF_X1)           9.85

Path reported is four, why? Here, I want to give you one more hint – Check number of flops associated per clock group. 😊

Below scenario, can help you to understand more clearly. Here I have created 4 clock groups

CASE4:
create_clock -name ck1 -period 10 {clk1}
create_clock -name ck2 -period 10 {clk2}
create_clock -name ck3 -period 10 {clk3}
create_clock -name ck4 -period 10 {clk4}
set_input_delay -clock ck1 0 {in1}
set_input_delay -clock ck2 0 {in2}
set_input_delay -clock ck3 0 {in3}

report_checks -format summary -path_group {ck1 ck2 ck3 ck4} -group_count 1

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
in1 (input)                 r1/D (DFF_X1)           9.85
in2 (input)                 r2/D (DFF_X1)           9.85
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.22
r2/Q (DFF_X1)           r4/D (DFF_X1)           9.24

report_checks -format short -path_group {ck1 ck2 ck3 ck4} -group_count 1

Startpoint: in1 (input port clocked by ck1)
Endpoint: r1 (rising edge-triggered flip-flop clocked by ck1)
Path Group: ck1
Path Type: max

Startpoint: in2 (input port clocked by ck2)
Endpoint: r2 (rising edge-triggered flip-flop clocked by ck2)
Path Group: ck2
Path Type: max

Startpoint: r2 (rising edge-triggered flip-flop clocked by ck2)
Endpoint: r3 (rising edge-triggered flip-flop clocked by ck3)
Path Group: ck3
Path Type: max

Startpoint: r2 (rising edge-triggered flip-flop clocked by ck2)
Endpoint: r4 (rising edge-triggered flip-flop clocked by ck4)
Path Group: ck4
Path Type: max

Here 4 paths are reported since we have 4 clock groups so one path from each clock group is reported when group_count is 1.

For group_count = 2

report_checks -format summary -path_group {ck1 ck2 ck3 ck4} -group_count 2

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
in1 (input)                 r1/D (DFF_X1)           9.85
in2 (input)                 r2/D (DFF_X1)           9.85
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.22
r2/Q (DFF_X1)           r4/D (DFF_X1)           9.24

You are expecting here 2 paths from each clock group that is total 8 paths, but only 4 paths are present in the reporting. WHY? I am sure by now, it’s easy for you to understand the reason of that. Like I gave hint last time – Flops per clock group. 😊
Now, do you think Flops per clock group is the answer or there is something else behind this. Or may be any other technical term or terminology. That you can find out in our next article, where we are going to discuss one more option and that’s going to help you to understand this very well.

-By Surabhi Singh
(Btech-EC:- 2019 Passout)
(ABES Engineering College)

-Supervised By Puneet Mittal
(Founder & Director)
(VLSI Expert Private Limited)

STA Tool Command - report_timing -max_paths_count (OpenSTA -group_count) : Part 1

As, I have shared last time that in this series of articles, we are going to discuss about the different command of STA Tools along with the concepts. We have used OpenSTA which is an open source tool and can be downloaded from OpenSTA. It’s commands are similar to Primetime (Industry standard tool). By using OpenSTA you can understand the working of tool properly. Here, I have made some of the comparison between the commands of Primetime & OpenSTA (which I am going to use in another few articles). The command which I have selected is report_timing (in Primetime) & report_checks (in OpenSTA). The report_checks / report_timing command reports paths in the design

Primetime	OpenSTA
report_timing [-group group_name][-max_paths count][-nworst paths_per_endpoint]	report_checks [-path_group group_names][-group_count path_count][-endpoint_count endpoint_path_count]
group group_name:Specifies the path groups from which timing paths are selected for reporting based on other specified options for reports.	path_group: List of path group names to report. All path groups are reported if this option is not specified
max_paths count:Specifies the number of paths to be reported per path group	group_count: The number of paths to report in each path group
nworst paths_per_endpoint: Specifies the number of paths to be reported per endpoint per path group	endpoint_count: The number of paths to report for each endpoint

In the previous Article, we have discussed in great detail about the report_timing -group (report_checks -path_group). How to create clock group and how tool by default reports only 1 report per path group. But now you can ask a question – what if you need all the possible reports with respect to 1 path group. We are going to discuss the same in this Article.

Below is an example to understand the reporting of the command (Same example which we have used last time).

In this circuit, depending upon the way we create path_group, we can get timing reports. But in general, there are several Timing path in any circuit. As a STA engineer, we need to analyse all of them.
Below commands and reporting structure can remind you by default options.

Case(1):

create_clock -name clk -period 10 {clk1 clk2 clk3}
set_input_delay -clock clk 0 {in1 in2}

report_checks -format summary -path_group clk

Startpoint           Endpoint        Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)        r3/D (DFF_X1)       9.43

report_checks -format short -path_group clk

Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Same reporting, I can achieve by adding one more switch with value 1 (i.e. -group_count 1)

Case(1):

create_clock -name clk -period 10 {clk1 clk2 clk3}
set_input_delay -clock clk 0 {in1 in2}

report_checks -format summary -path_group clk -group_count 1

Startpoint           Endpoint        Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)        r3/D (DFF_X1)       9.43

report_checks -format short -path_group clk -group_count 1

Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

If you have noticed the difference, we have used one more argument / switch group_count.

group_count The number of paths to report in each path group

But it’s not that simple. Let’s understand this command more in detail using different test cases and different scenerios.
In above example, only 1 path is reported with respect to clock group clk? Why ONE, because I have given group_count == 1. What if I give group_count = 2? let’s check

Case(1):

create_clock -name clk -period 10 {clk1 clk2 clk3}
set_input_delay -clock clk 0 {in1 in2}

report_checks -format summary -path_group clk -group_count 2

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.43
in1 (input)                r1/D (DFF_X1)           9.85

we obtain 2 worst reports from path group clk

Similarly, we can check for group_count = 3

report_checks -format summary -path_group clk -group_count 3

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.43
in1 (input)                r1/D (DFF_X1)           9.85
in2 (input)                r2/D (DFF_X1)           9.85

What if, I give group_count = 4? I am sure, you will say 4 paths should be reported. Let’s check

report_checks -format summary -path_group clk -group_count 4

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.43
in1 (input)                r1/D (DFF_X1)           9.85
in2 (input)                 r2/D (DFF_X1)           9.85

Here we see only 3 paths.... Why??

Let’s check for group_count = 5

report_checks -format summary -path_group clk -group_count 5

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------

r2/Q (DFF_X1)           r3/D (DFF_X1)           9.43
in1 (input)                 r1/D (DFF_X1)           9.85
in2 (input)                 r2/D (DFF_X1)          9.85

Here also only three paths. Why is this thing happening.

Let’s check for group_count = 6

report_checks -format summary -path_group clk -group_count 6

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.43
in1 (input)                 r1/D (DFF_X1)           9.85
in2 (input)                 r2/D (DFF_X1)           9.85

Here also the same,

I have summarized the result in the table

group_count	No. Of Reports
1	1
2	2
3	3
4	3
5	3
6	3
7	3
8	3
9	3
10	3

Now the question is although we have increased group_count but number of paths reported is three only? As per the definition, it should also increase. I am leaving his question to you right now and let’s see if you can think/guess something about this. Else we obviously discuss it later.

Let’s try to understand it by creating 2 different clock group and play with value of group_count.


Consider case(2) to understand group_count clearly

Command:
create_clock -name clk -period 10 {clk1 clk3}
create_clock -name clkc -period 10 {clk2}
set_input_delay -clock clk 0 {in1}
set_input_delay -clock clkc 0 {in2}

report_checks -format summary -path_group {clk clkc} -group_count 1

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.43
in2 (input)                r2/D (DFF_X1)           9.85

report_checks -format short -path_group {clk clkc} -group_count 1

Startpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Startpoint: in2 (input port clocked by clk)
Endpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Path Group: clkc
Path Type: max

Since group count is one therefore one path from each path group is reported i.e. one path from clock group clk and other from clock group clkc.

Let’s make group_count 2 and observe the changes in report

report_checks -format summary -path_group {clk clkc} -group_count 2

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.43
in1 (input)                 r1/D (DFF_X1)           9.85
in2 (input)                 r2/D (DFF_X1)           9.85

report_checks -format short -path_group {clk clkc} -group_count 2

Startpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Startpoint: in1 (input port clocked by clk)
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Startpoint: in2 (input port clocked by clk)
Endpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Path Group: clkc
Path Type: max

In this case we observe thee paths, two from the clock group clk and one from the clock group clkc
You must be thinking why only one path is reported from clock group clkc. Just think over it

Now, I’m increasing the group_count

report_checks -format summary -path_group {clk clkc} -group_count 3

Startpoint              Endpoint           Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)           r3/D (DFF_X1)           9.43
in1 (input)                 r1/D (DFF_X1)           9.85
in2 (input)                 r2/D (DFF_X1)           9.85

report_checks -format short -path_group {clk clkc} -group_count 3

Startpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Startpoint: in1 (input port clocked by clk)
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Startpoint: in2 (input port clocked by clk)
Endpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Path Group: clkc
Path Type: max

We should get here 3 paths from clock group clk and three path from clock group clkc but overall we are getting only three paths
why?? Still not able to get / guess answer? 😊

Again, I am trying summarize my analysis

I have summarized the result in the table

Clock Group	group_count	Total No. Of Reports
2	1	2
2	2	3
2	3	3
2	4	3
2	5	3
2	...	3

Let’s discuss another circuit and see if you can figure out but that we will discuss in part 2 of this article. :)

-By Surabhi Singh
(Btech-EC:- 2019 Passout)
(ABES Engineering College)

-Supervised By Puneet Mittal
(Founder & Director)
(VLSI Expert Private Limited)

10 Employee Awards To Boost Morale At The Workplace

Employees function as the backbone of any company and making sure that employee satisfaction is at its highest is incredibly important for the smooth functioning of a corporation. Employees who come in day in and day out are generally dedicated to improving the manner in which the company works. They are one of the main reasons why the company has been able to function as intended. For employers, making sure that you are giving your employees all that they need to perform their jobs well is incredibly important. 

One way of making your employees feel appreciated in the workplace is to hand out awards. When running a company, you always want your employees to feel like they have a special place at the company. This encourages individuals to do their work better. While this is important for companies, it is essential for employers to take a few additional steps that their employees will respond well to. 

Hosting an awards ceremony and honoring your employees is a brilliant idea for improving employee engagement. It is incredibly important for brands to understand the positive impact that these kinds of activities can have, which is why it is important for companies to implement this on a regular basis. If you are thinking of handing out employee awards or custom trophies at a company, there are a number of routes that you can take in this regard. 

No matter what kind of company you operate as, be it an electronics company or even a paper manufacturing unit, partaking in employee awards ceremonies can help boost morale at the workplace, and can improve the employee satisfaction at a workplace. Here are some of the employee award ideas you can use when trying to honor the people working at the company:

1. Customer Service Performance Award

If you have any kind of customer service department at your company, offering an award for customer service performances can help boost morale, and can make customer service representatives feel more appreciated. 

2. Chief Happiness Director Award

There are always employees at the workplace that bring a certain amount of joy into every room that they enter, and honoring these employees is incredibly essential.

3. First Class Service Award

For companies operating within the service category, employees who have had the highest rating in terms of their services can be given an award for their good work.

4. Hall of Fame Award

The Hall of Fame Award is one that can be given to employees who have been working at a company for a long period of time and who have made significant contributions.

5. Top Performer Award

The Top Performer Award should be given to individuals who have made a good impression on the company, as well as the clients, and who have had a good reputation for the work that they do.

6. An Employee of the Month Award

An Employee of the Month Award is one of the most commonly found awards and is great for honoring employees on a regular basis. The employee of the month award is generally given to individuals who have had an outstanding performance over the past month of work.

7. Leaderboard Award

For companies that have operations that can integrate a scoring system, having a Leaderboard Award can motivate employees to work harder to rise up the ranks and earn their spot, thereby helping the company operate in a more efficient manner.

8. Retirement Award

Honoring people who are retiring from the company is important because of the contribution they have made. It is important to improve the image of a company.

9. Team Leader Award

The Team Leader Award is mainly for those who have worked in groups and who have exhibited strong leadership qualities. This award can also encourage others to step up and work as leaders in a group situation.

10. Top Collaborator Award

Top Collaborator Award can be given to those who work well as a team, and who have had a significant impact on the people that they work with and the projects that they work on. This can help encourage individuals to work better with their colleagues and can give them the impetus that they need to work hard in their positions.

STA Tool Command - report_timing -group (OpenSTA-path_group)

We are going to start a new series where we are going to discuss about the different command of STA Tools along with the concepts. I have received a lot of requests about the tool understanding and their features. After discussing with them - I have figured out - problem is not HandsOn but it's all about mapping of different concepts (fundamental & Basics) with the Tool commands. So, in this series - we will make sure that every command - every option we use in detail and help you to visualize that with the help of small test cases.
Using any Industry standard Tool like Primetime or Tempus and doing all the analysis on that - It may be easy for that but those who don't have access these articles again become as Theoretical article. I would like everyone to Try at home. So, My team is using OpenSource Tool which is similar to Primetime upto a certain limit. We will share command mapping table between OpenSource tool Vs Industry standard tool (which can help you in case you have access of Industry Standard Tool). In general, we will use Opensource tool's command and reporting structure in rest of the article.

We have created / generated our own Test cases and using library data available along with OpenSource Tools. So, dnt worry - You can also Download this and try at your place. :)

OpenSTA (One of the OpenSource tool) can be downloaded from OpenSTA, have commands which works similarly as the commands of Primetime. By using OpenSTA you can understand the working of tool properly. Here, I have made some of the comparison between the commands of Primetime & OpenSTA (which I am going to use in another few articles). The command which I have selected is report_timing (in Primetime) & report_checks (in OpenSTA). The report_checks / report_timing command reports paths in the design

Primetime	OpenSTA
report_timing [-group group_name][-max_paths count][-nworst paths_per_endpoint]	report_checks [-path_group group_names][-group_count path_count][-endpoint_count endpoint_path_count]
group group_name:Specifies the path groups from which timing paths are selected for reporting based on other specified options for reports.	path_group: List of path group names to report. All path groups are reported if this option is not specified
max_paths count:Specifies the number of paths to be reported per path group	group_count: The number of paths to report in each path group
nworst paths_per_endpoint: Specifies the number of paths to be reported per endpoint per path group	endpoint_count: The number of paths to report for each endpoint

Below is an example to understand the reporting of the command

In this circuit, we have 3 flipflops & the clock clk1, clk2, clk3 of these flops are related to one single clock clk. We are going to do the grouping of these clocks using the following command.

create_clock -name clk -period 10 {clk1 clk2 clk3}

Here, 10 is the period for each clock and clk is the name of the clock group. To understand why we are doing the grouping the clocks and what's significant of that, let's understand the use model of that.

path_group is one of the option which help the tool/categorize/filter different reports based on clock group. To understand argument/option path_group, below are few reports.

Case(1):

create_clock -name clk -period 10 {clk1 clk2 clk3}

report_checks -format summary -path_group clk

Startpoint           Endpoint        Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)        r3/D (DFF_X1)       9.43

report_checks -format short -path_group clk

Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Note:

• -format summary shows only the summary of the path including startpoint, endpoint and the slack.
• -format_short shows the start point, end point, path group and path type.

Only one path is reported here. Can you guess why?
It is because this is the worst path of clock group clk and if you notice in the command, path group mention is clk. That’s why worst path of clock group clk is reported.

Note: By default tool will report the worst path.

If I create two path group then what will happen?
To understand this let’s create two clock group, one with name clk and other with clkc

Case(2)::

create_clock -name clk -period 10 {clk1 clk3}
create_clock -name clkc -period 10 {clk2}
set_input_delay -clock clk 0 {in1 in2}

report_checks -format summary -path_group {clk clkc}

Startpoint        Endpoint        Slack
----------------------------------------------------------------------------
r2/Q (DFF_X1)        r3/D (DFF_X1)        9.43
in2 (input)        r2/D (DFF_X1)       9.85

report_checks -format short -path_group {clk clkc}

Startpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Startpoint: in2 (input port clocked by clk)
Endpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Path Group: clkc
Path Type: max

So, we can see here two path are reported, the question is which are they?
Since we have made two clock groups that’s why one worst path from each clock group is reported

To understand the concept of path_group let’s take one more example

Case(1):

create_clock -name clk -period 10 {clk1 clk2 clk3 clk4}
set_input_delay -clock clk 0 {in1 in2 in3}

report_checks -format summary -path_group clk

Startpoint        Endpoint        Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)        r3/D (DFF_X1)        9.22

report_checks -format short -path_group clk

Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

We can see one path (worst) in reported of path group clk since we create a single clock group of name clk.

Case(2):

create_clock -name clk -period 10 {clk1 clk3}
create_clock -name clkc -period 10 {clk2 clk4}
set_input_delay -clock clk 0 {in1 in2 in3}

report_checks -format summary -path_group {clk clkc}

Startpoint        Endpoint        Slack
--------------------------------------------------------------------------------
r2/Q (DFF_X1)        r3/D (DFF_X1)        9.22
r2/Q (DFF_X1)        r4/D (DFF_X1)        9.24

report_checks -format short -path_group {clk clkc}

Startpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Endpoint: r4 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Startpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Endpoint: r4 (rising edge-triggered flip-flop clocked by clkc)
Path Group: clkc
Path Type: max

Here I have made two clock group, one is clk which is related to clock clk1 & clk3, the other is clkc which is related to clock clk2 & clk4. So one path (worst) from both the clock group is reported. Now if I create 3 clock groups then what will happen-

Case(3)::

create_clock -name clk -period 10 {clk1 clk3}
create_clock -name clkc -period 10 {clk2}
create_clock -name clck -period 10 {clk4}
set_input_delay -clock clk 0 {in1 in2 in3}

report_checks -format summary -path_group {clk clkc clck}

Startpoint        Endpoint        Slack
--------------------------------------------------------------------------------

r2/Q (DFF_X1)        r4/D (DFF_X1)        9.24
r2/Q (DFF_X1)        r3/D (DFF_X1)        9.22
in2 (input)        r2/D (DFF_X1)        9.85

report_checks -format short -path_group {clk clkc clck}

Startpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Endpoint: r4 (rising edge-triggered flip-flop clocked by clck)
Path Group: clck
Path Type: max

Startpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Startpoint: in2 (input port clocked by clk)
Endpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Path Group: clkc
Path Type: max

I am sure now to understand how three reports are generated. One with respect to each clock group.

Let’s try one more case-

report_checks -format short -path_group {clkc clck}

Startpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Endpoint: r4 (rising edge-triggered flip-flop clocked by clck)
Path Group: clck
Path Type: max

Startpoint: in2 (input port clocked by clk)
Endpoint: r2 (rising edge-triggered flip-flop clocked by clkc)
Path Group: clkc
Path Type: max

You should know the reason for this reporting.

In the next article we will discuss about more interesting command option (OpenSTA -group_count | Primetime -max_paths) of report_checks | report_timing.

-By Surabhi Singh
(Btech-EC:- 2019 Passout)
(ABES Engineering College)

-Supervised By Puneet Mittal
(Founder & Director)
(VLSI Expert Private Limited)