In the last few articles (PART 1, PART 2 and PART 3), we have discussed the following things
- SDF different sections and different construct - In PART 2
- Cell Section details - In PART 3
- Delay Details in SDF - In PART 4
Lets discuss the below circuit.
As a part of SDF, if you remember, we have discussed in PART 2 - that there is a HEADER section, Then CELL Section. In our circuit, there are 5 instance of Cells - r1, r2, r3, u1 & u2. These cells are mapped with Library as (This information you can get from .lib or from .v file)
r1, r2 and r3 -> DFF_X1
u1 -> BUF_X1
u2 -> AND2_X1
Header Section - marked as RED Color
CELL Section where we are talking about interconnect Delays - marked as GREEN color
CELL Section with respect to Flipflops - marked as BLUE color
CELL Section with respect to Buffer - marked as BLACK color
CELL Section with respect to AND gate - marked as LIGHT GREEN color.
And that's all the construct.
(DELAYFILE
(SDFVERSION "OVI 2.1")
(DESIGN "vlsiexpert")
(DATE "Thu Dec 12 20:33:26 2019")
(VENDOR "vlsiexpert")
(PROGRAM "customized")
(VERSION "01")
(DIVIDER /)
(VOLTAGE 2.25:2.25:2.25)
(PROCESS "1.000:1.000:1.000")
(TEMPERATURE 125.00:125.00:125.00)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "vlsiexpert")
(INSTANCE)
(DELAY
(ABSOLUTE
// Offset in1 vs in2, rise vs fall arrivals so results are deterministic.
(INTERCONNECT in1 r1/D (0.011:0.011:0.011) (0.01:0.01:0.01))
(INTERCONNECT in2 r2/D (0.021:0.021:0.021) (0.02:0.02:0.02))
(INTERCONNECT clk1 r1/CK (0.0:0.0:0.0) (0.0:0.0:0.0))
(INTERCONNECT clk2 r2/CK (0.0:0.0:0.0) (0.0:0.0:0.0))
(INTERCONNECT clk3 r3/CK (0.0:0.0:0.0) (0.0:0.0:0.0))
(INTERCONNECT r1/Q u2/A1 (0.0:0.0:0.0) (0.0:0.0:0.0))
(INTERCONNECT r2/Q u1/A (0.0:0.0:0.0) (0.0:0.0:0.0))
(INTERCONNECT u1/Z u2/A2 (0.0:0.0:0.0) (0.0:0.0:0.0))
(INTERCONNECT u2/ZN r3/D (0.0:0.0:0.0) (0.0:0.0:0.0))
(INTERCONNECT r3/Q out (0.0:0.0:0.0) (0.0:0.0:0.0))
)
)
)
(CELL
(CELLTYPE "DFF_X1")
(INSTANCE r1)
(DELAY
(ABSOLUTE
(IOPATH CK Q (1:1:1) (1.1:1.1:1.1))
)
)
(TIMINGCHECK
(SETUP D (posedge CK) (.5:.5:.5))
(HOLD D (posedge CK) (.1:.1:.1))
(PERIOD (posedge CK) (1.0:2.0:3.0))
)
)
(CELL
(CELLTYPE "DFF_X1")
(INSTANCE r2)
(DELAY
(ABSOLUTE
(IOPATH CK Q (1:1:1) (1.1:1.1:1.1))
)
)
(TIMINGCHECK
(SETUP D (posedge CK) (.5:.5:.5))
(HOLD D (posedge CK) (.1:.1:.1))
(PERIOD (posedge CK) (1.0:2.0:3.0))
)
)
(CELL
(CELLTYPE "DFF_X1")
(INSTANCE r3)
(DELAY
(ABSOLUTE
(IOPATH CK Q (1:1:1) (1.1:1.1:1.1))
)
)
(TIMINGCHECK
(SETUP D (posedge CK) (.5:.5:.5))
(HOLD D (posedge CK) (.1:.1:.1))
(PERIOD (posedge CK) (1.0:2.0:3.0))
)
)
(CELL
(CELLTYPE "BUF_X1")
(INSTANCE u1)
(DELAY
(ABSOLUTE
(IOPATH A Z (1:1:1) (1.1:1.1:1.1))
)
)
)
(CELL
)
(CELLTYPE "AND2_X1")
(INSTANCE u2)
(DELAY
(ABSOLUTE
(IOPATH A1 ZN (1:1:1) (1.1:1.1:1.1))
(IOPATH A2 ZN (1:1:1) (1.1:1.1:1.1))
)
)
)
Note:
- In the Interconnect Delay, SDF has delays of all 10 wires/interconnects.
- Input port to Reg input D pin (in1 to r1/D , in2 to r2/D)
- Clock_source to Clock_input pin of Register (clk1 to r1/CK, clk2 to r2/CK, clk3 to r3/CK)
- Reg output Q pin to Output port (r3/Q to out)
- All internal combinational nets
- For all flipflop we have all required info which we need from .Lib
- Clock to Q delay
- Setup and Hold constraint
- Positive Edge or Negative Edge triggered Flipflop
- Clock Time period information
- For all other logic cells, we have following information
- Cell Rising and Falling delay
- Cell - Min, Max and Typical Delay
- Input pin - output pin specific delay (also know as ARC delay - like in case of AND - a->y and b-y)
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