Latch based Timing Analysis - Part 1

This series we are starting for Latch based Timing Analysis. In case of Latch, there are lot of basic concepts which are similar to Flipflop based Timing but still we get confuse a lot of time, I am going to try my best to clarify that.

Let's first try to understand Flipflop Vs Latch when we are doing Timing analysis. You will see everything is almost same.

In the above circuit you can see that everything is same, only difference - LATCH is placed in place of FLIPFLOP. Apart of this - understanding of Launch Latch and Capture Latch is same.

• Launch Latch - The Latch which is going to launch the data.
• Capture Latch - The Latch which is going to capture the data.

Below comparison also give you understanding between different other terminologies. Like Capture clock path, Launch clock path, Arrival data path, Required path.

Apart of this - remember - all the Timing Terminologies are same in case of Latch. Only difference is the way you are going to apply these concepts. Now, question come why? - because there is a difference in the functionality of the Flipflop and Latch.

Latch is level Triggered and Flipflop is Edge Triggered - this is something everyone know. More specifically - A latch is a level-sensitive storage cell that is transparent to signals passing from the D input to output Q when it is enabled. Latch holds the values of D on Q as Latch become disable. Depending on the polarity of the enable input, Latches are of Positive or Negative level. Flip-flop is an edge-triggered device that changes state at Q as per D on the rising or falling edge of an enable signal. Flipflop holds the values of D until the next respective (rising or falling) edge of the enable signal.

But when I have asked couple of people what will happen in case of Latch at the edges - so either they become confuse or don't have clear understanding. Try to understand this from the following waveform (Launch and Capture clock of latch means - clock which is enable Launch and Capture Latch).

Lets understand this …

Eligibility of Launch Latch (which is Positive level latch) to launch data started the moment there is a rising edge (enable signal making transaction from Negative level to Positive level). It can launch the data continuously (means passing the data from D to Q or say created a continuous path between D and Q) till latch is disabled. This disable activity started at falling edge (the moment enable signal making transaction from Positive Level to Negative level). Now, try to understand the "First edge used for Launch" and "Last edge used for Launch" in the above waveform diagram.

Let's take the example of Data launch at the first edge of the Launch waveform -

1. Data A (red data in above fig) - Delay between the Launch and Capture Latch is very less, then data can be capture at the first positive Level itself at the Capture waveform (as showing in the figure)
• Remember - this is Latch and Latch is transparent at level. In case of Flipflop - data capture only at the edges.
2. Data B (Orange data in above fig) - Delay is significant. Data can reach at D pin of Capture Latch when Latch was disabled. So now, it can only be capture next time when capture Latch is going to enable. Since Data is already present (before the Capture Latch enable), eligibility of capture Latch (which is Positive level latch) to capture data started the moment there is a rising edge (enable signal making transaction from Negative level to Positive level).
• Remember - If you compare this scenario you will find no difference between Latch and Flipflop. Because both are launching the Data at Rising clock edge and both will capture the data at Rising clock edge. :)
3. Data C (green data in the above fig) - Delay is more. It's reaching at D pin of Capture Latch when latch become enable already (second time). Since Latch is already enable, data can easily capture by Latch and passes to Q pin at the same time.
• Remember - If we want that data should be captured by latch at this level only (when capture latch enable second time), then we have to make sure that data should reach at D pin before the Latch disable - means before Falling edge of clock :).
• Remember - If this is the case of Flipflop - then either we have to reduce the delay or we have to make this path as multi-cycle path. But In Latch, still no need of multicycle concept. :)

Now, try to understand the "First edge used for Capture" and "Last edge used for Capture" concept in the above waveform diagram.

If you can understand above diagram, I can say that Latch can start sampling data from the rising edge (or falling edge) itself and continue sampling till the respective falling edge (or rising edge). And Flipflop can only sample the data "at" Rising edge or Negative edge. Both holds the data when they are disable (Latch disable at level and Flipflop disable just after triggering level).

Generally designers prefer flip flops over latches because of this edge-triggered property, which makes their life easy to do analysis and interpretation the design. Latch based design give you a lot of flexibility but remember nothing comes free. You have to pay your TIME and ATTENTION for that. :)

E.g -

1. Latch-based designs are preferred in case of clock frequency in GHz (in high-speed designs). In flip-flop-based high-speed designs, maintaining clock skew is a problem, but latches ease this problem.
2. In the design, slowest path decide the frequency of the design - means at which frequency design can work correctly.
3. Latch based design are more susceptible from process variation.

Now, Lets try to understand below diagram. I am sure, now it's very simple to understand. Different Data are launched between First edge and Last edge used for Launching purpose of X1 level from Launch Latch. As per our expectation, these data should be captured by X2 level at capture Latch (Between first and Last edge used for capturing purpose). If any Data don't reach by the time of Falling edge of Level X2 at capture Latch, we will consider that as not Captured. Now, try to correlate this uncaptured data with Violation of data (what ever we have discussed in Setup and Hold time/violation of Flipflop).

In the next article, we will discuss the Setup/Hold and Delay of Latch. Stay Tuned :)

How To Read SDF (Standard Delay Format) - Part5

In the last few articles (PART 1, PART 2 and PART 3), we have discussed the following things

• SDF different sections and different construct - In PART 2
• Cell Section details - In PART 3
• Delay Details in SDF - In PART 4

Now. it's the time to discuss about the SDF using an example.

Lets discuss the below circuit.

As a part of SDF, if you remember, we have discussed in PART 2 - that there is a HEADER section, Then CELL Section. In our circuit, there are 5 instance of Cells - r1, r2, r3, u1 & u2. These cells are mapped with Library as (This information you can get from .lib or from .v file)

r1, r2 and r3 -> DFF_X1
u1 -> BUF_X1
u2 -> AND2_X1

Header Section - marked as RED Color
CELL Section where we are talking about interconnect Delays - marked as GREEN color
CELL Section with respect to Flipflops - marked as BLUE color
CELL Section with respect to Buffer - marked as BLACK color
CELL Section with respect to AND gate - marked as LIGHT GREEN color.

And that's all the construct.

(DELAYFILE
  (SDFVERSION "OVI 2.1")
  (DESIGN "vlsiexpert")
  (DATE "Thu Dec 12 20:33:26 2019")
  (VENDOR "vlsiexpert")
  (PROGRAM "customized")
  (VERSION "01")
  (DIVIDER /)
  (VOLTAGE 2.25:2.25:2.25)
  (PROCESS "1.000:1.000:1.000")
  (TEMPERATURE 125.00:125.00:125.00)
  (TIMESCALE 1ns)

  (CELL
   (CELLTYPE "vlsiexpert")
   (INSTANCE)
   (DELAY
    (ABSOLUTE
// Offset in1 vs in2, rise vs fall arrivals so results are deterministic.
     (INTERCONNECT in1 r1/D (0.011:0.011:0.011) (0.01:0.01:0.01))
     (INTERCONNECT in2 r2/D (0.021:0.021:0.021) (0.02:0.02:0.02))
     (INTERCONNECT clk1 r1/CK (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT clk2 r2/CK (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT clk3 r3/CK (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT r1/Q u2/A1 (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT r2/Q u1/A (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT u1/Z u2/A2 (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT u2/ZN r3/D (0.0:0.0:0.0) (0.0:0.0:0.0))
     (INTERCONNECT r3/Q out (0.0:0.0:0.0) (0.0:0.0:0.0))
    )
   )
 )

 (CELL
  (CELLTYPE "DFF_X1")
  (INSTANCE r1)
  (DELAY
   (ABSOLUTE
    (IOPATH CK Q (1:1:1) (1.1:1.1:1.1))
   )
  )
  (TIMINGCHECK
   (SETUP D (posedge CK) (.5:.5:.5))
   (HOLD D (posedge CK) (.1:.1:.1))
   (PERIOD (posedge CK) (1.0:2.0:3.0))
  )
 )

 (CELL
  (CELLTYPE "DFF_X1")
  (INSTANCE r2)
  (DELAY
   (ABSOLUTE
    (IOPATH CK Q (1:1:1) (1.1:1.1:1.1))
   )
  )
  (TIMINGCHECK
   (SETUP D (posedge CK) (.5:.5:.5))
   (HOLD D (posedge CK) (.1:.1:.1))
   (PERIOD (posedge CK) (1.0:2.0:3.0))
  )
 )

 (CELL
  (CELLTYPE "DFF_X1")
  (INSTANCE r3)
  (DELAY
   (ABSOLUTE
    (IOPATH CK Q (1:1:1) (1.1:1.1:1.1))
   )
  )
  (TIMINGCHECK
   (SETUP D (posedge CK) (.5:.5:.5))
   (HOLD D (posedge CK) (.1:.1:.1))
   (PERIOD (posedge CK) (1.0:2.0:3.0))
  )
 )

 (CELL
  (CELLTYPE "BUF_X1")
  (INSTANCE u1)
  (DELAY
   (ABSOLUTE
    (IOPATH A Z (1:1:1) (1.1:1.1:1.1))
   )
  )
 )

 (CELL
  (CELLTYPE "AND2_X1")
  (INSTANCE u2)
  (DELAY
   (ABSOLUTE
    (IOPATH A1 ZN (1:1:1) (1.1:1.1:1.1))
    (IOPATH A2 ZN (1:1:1) (1.1:1.1:1.1))
   )
  )
 )

)

Note:

• In the Interconnect Delay, SDF has delays of all 10 wires/interconnects.
• Input port to Reg input D pin (in1 to r1/D , in2 to r2/D)
• Clock_source to Clock_input pin of Register (clk1 to r1/CK, clk2 to r2/CK, clk3 to r3/CK)
• Reg output Q pin to Output port (r3/Q to out)
• All internal combinational nets
• For all flipflop we have all required info which we need from .Lib
• Clock to Q delay
• Setup and Hold constraint
• Positive Edge or Negative Edge triggered Flipflop
• Clock Time period information
• For all other logic cells, we have following information
• Cell Rising and Falling delay
• Cell - Min, Max and Typical Delay
• Input pin - output pin specific delay (also know as ARC delay - like in case of AND - a->y and b-y)

How To Read SDF (Standard Delay Format) - Part4

In the last few articles (PART 1, PART 2 and PART 3), we have discussed the following things

• What is SDF and what information it contain?
• Construct of SDF (2 Section – Header and CELL)
• Header Section contain general information about the Tool which is used to create/generate the SDF and the Design related information (like Design name, Process, Voltage, Temperature of the design for which SDF is generated).
• Cell Section can be multiple in the SDF file. These CELL section can represent to a specific Primitive cell (standard Cell) or a region of the design (Blocks) or any instance in a hierarchy.
• Cell section has 3 different sub-section – CELLTYPE , INSTANCE, Timing specification section.
• Timing specification section contain actual timing data associated with that cell. There are four types of timing specifications that are identified by the DELAY, TIMINGCHECK, TIMINGENV, and LABEL keywords.
• DELAY: Specify the delay related information for back-annotation.
• TIMINGCHECK: Specify Timing checks limit data for back-annotation
• TIMINGENV: Specify timing environment data and constraint data for forward-annotation.
• LABEL: Set the values of timing model variables upon that delays and timing constraint values depend

In this Article, we will discuss more details about the DELAY construct. This is the most important part of the SDF. It’s a Standard Delay format – so it’s important to have a separate Article only for Delay.

Delay values are defined in SDF in the form of list. This list can have 1,2,3,6 or 12 pairs. These pairs are corresponds to the transition of the signal at the output port. The sequence of those transition is fixed and described in the following table.

Note:

• If only 1 pair is present in the delay list then it’s same for all 12 transition.
• There are chances that in SDF, any pair has NULL value. It is consider as placeholder for that particular transition. Means the stage where SDF is created, the delay info corresponding to that transition is not available and later it can be filled.

Example 1: (IOPATH i3 o1 () () (2:4:5) (4:5:6) (2:4:5) (4:5:6))

In the above example, there is no delay value present for 0->1 and 1->0 transition.

Type of Delay:

There are 2 types of Delay based on how it will be annotated into the design.

Incremental Delay: If any delay value is defined under this category it means it will add SDF value into the Delay present in the design (at the time you are trying to annotate SDF delay).

Absolute Delay: If any delay value is defined under this category it means it will replace the Delay present in the design (at the time you are trying to annotate SDF delay).

Category of Delay in SDF:

Delay in the SDF can be any of the following category.

1) Input-output path Delay:

• Represent the delays on a legal path from an input/bidirectional port to an output/bidirectional port of a device. Each delay value shall be associated with a unique input_port - output_port pair.
• Input or a bidirectional port can have an edge identifier.
• No edge Identifier can be present in case of output or a bidirectional port.
• Representation of Delay values are in the same fashion as explained in above.
• Construct used in SDF : IOPATH

Note:

• For in1, positive edge identifier is specified.
• These Delay are absolute (ABSOLUTE) in nature. Means it’s going to replace any delay specified in Timing models for these paths under specified transitions.
• For in3, delay values are NULL for first 2 transition (0->1 and 1->0). It means for these transition, Delay values are unchanged (it will remain as-it-is as in the timing models).

2) Conditional path delays:

Now if you want to apply a particular condition before applying a particular path delay, we can use this method. The conditional path delay shall specify conditional (state-dependent) input-to-output path delays.
There are 2 ways to apply the conditions

• If a Particular Condition met, then apply the Delay value
• The annotator must locate in the timing model a path delay with conditions matching those specified in the SDF file. Other path delays between the same ports but with different conditions shall not receive the data.
• The expression shall evaluate to a logical signal, rather than a boolean. The analysis tool shall treat a logical zero as FALSE and any other logical value (1, X, or Z) as TRUE. A particular conditional path delay in the timing model shall be used only if the condition is TRUE.
• Use the SDF Construct : COND
• If a Particular Condition doesn’t met, then apply the Delay value
• The delay values specified in SDF shall be used if none of the conditions specified for the path in the model are TRUE but a signal must still be propagated over the path.
• Use the SDF construct: CONDELSE

3) Port Delay:

• Port delay specify the interconnect delay (actual or estimated) that are modelled as delay at input port.
• Use the SDF Construct: PORT

Note: Above delay is applied same for net between “y” and “c.r1.a” and “c.r2.a”.

4) Interconnect Delay

• The interconnect delay shall specify the propagation delay across a net connecting a driving module port (the source) to a driven module port (the load).
• Either or both ports can be bidirectional. Both source and load ports for the delay path shall be specified.
• Use the SDF Construct: INTERCONNECT

5) Net Delay:

• The net delays shall specify the propagation delays from all sources to all loads of a net.
• Neither start nor end points for the delay path are specified, and the delays from all the source ports to all the destination ports will have the same value.
• Use the SDF Construct: NETDELAY

There are other SDF construct also but I am not discussing them here. The reason being – it will increase the length of the Article & looks to me that’s not required right now.;) For the detail info, you can refer the “IEEE standard for Standard Delay format for electronic design format”. Most of my content also have same reference.

Apart of this – Most important thing is SDF constructs are originally targeted for annotation to tools using the Verilog language, so many SDF constructs are analogous to those in Verilog specify blocks. Those already familiar with the Verilog specify block will find many of the SDF constructs familiar. So it’s very easy for those who are champ in Verilog. 

In the Next Article, we will take a circuit and respective SDF, to give you an idea - how to read SDF with respect to a circuit.