Logic Level & Noise Margin

Today, we will talk about the logic levels and what’s all this. I came across several students and realize that they are struggling big time to understand the Logic level, Input-output logic level and all.

Let’s start with above known logic level diagram. Here, you can see that range of signal for Logic 0 is 0V to 1V and similarly for Logic 1 – It’s 2V to 3V, Till this point, everyone is (should be) clear. But the moment I ask what’s between Logic 1 and Logic 0 – confusion start. Few says it’s Undefined region and few smart kid says – it’s Noise Margin. :) The moment I ask them to define or provide more insight about this Noise region (as per smart kid), none of them able to define it. :)

In this article, we will discuss about this region and more related concepts.

Remember, everything above is with respect to Positive Logic Level and same we will discuss through out this article. To understand what’s Positive Logic Level and Negative Logic Level – please refer Digital Basic (Logic Gates – Part a).

Voltage Logic Level (Input/Output)

Let's try to understand the Logic Level at the Input and Output of a Gate.

Logic Level at the input of the Gate is known as Input Logic Level and corresponding voltage range as:

• Logic 1: Start from V_IH (Minimum Input Voltage for Logic High) and Ends at VDD
• Logic 0: Start from VSS and Ends at V_IL (Maximum Input Voltage for Logic Low)

Logic Level at the output of the Gate is known as Output Logic Level and corresponding voltage range as:

• Logic 1: Start from V_OH (Minimum Output Voltage for Logic High) and Ends at VDD
• Logic 0: Start from VSS and Ends at V_OL (Maximum Output Voltage for Logic Low)

Below Figure, can help you to understand what I am talking about...

Now, as a difference, you can see both (Input and Output Logic levels) have voltage range for Logic 1 & Logic 0. So Next question is:

• Are V_OH = V_IH and V_OL = V_IL ??
• What's the relationship between different voltage level? ??

You have to justify your answer with proper reason. Let me try from my side :) with logical explanation.

In above fig, 2 NAND gates (1 & 2) are connected back to back. Let’s consider both NAND gates are 100% similar. If, NET Delay is Zero, Our Expectation is :: Any signal at the output of “Gate1 with Logic 1” should be identify as “Logic 1 at the Input of Gate2”. Same goes with Logic 0 also. Let's try to understand with example (if helps you to understand more clearly).

Scenario 1: V_OH < V_IH ; VDD = 5V, V_OH = 3V, V_IL = 1V, V_IH = 4V

• Output Logic 1
• Voltage range of Output Logic 1 is between 3V to 5V.
• It means any signal with a voltage value between 3V and 5V is consider as Logic 1 at the output pin of Gate1.
• Input Logic 1
• Voltage range of Input Logic 1 is between 4V to 5V.
• It means any signal with a voltage value between 4V and 5V is considered as Logic 1.
• Any signal below 4V is NOT considered as part of Logic 1.

Now, assume that a signal coming out from Gate 1 has voltage = 3V. It’s consider as part of Logic 1 for Gate 1 but when this signal propagate and reach at input of Gate 2, it will be nowhere (Means neither 1 nor 0 because voltage range of Logic 1 start from 4V and voltage range of Logic 0 ends at 1V).
So, in this Ideal scenario (Ideal means No Net Voltage Drop), to capture the Logic 1 at the input of Gate 2, Output voltage of Gate 1 for Logic 1 should have below condition.

V_OH ≥ V_IH

Scenario 2: V_OL ≥ V_IL ; VSS = 0V, V_OL = 2V, V_IL = 1V, V_IH = 4V

• Output Logic 0
• Voltage range of Output Logic 0 is between 0V to 2V.
• It means any signal with a voltage value between 0V and 2V is consider as Logic 0.
• Input Logic 0
• Voltage range of Input Logic 0 is between 0V to 1V.
• It means any signal with a voltage value between 0V and 1V is considered as Logic 0.
• Any signal above 1V is not considered as part of Logic 0.

Now, assume that a signal coming out from Gate 1 has voltage = 2V. It’s consider as part of Logic 0 for Gate 1 but when this signal propagate and reach at input of Gate 2, it will be nowhere (Means neither 1 nor 0 because voltage range of Logic 0 ends at 1V and voltage range of Logic 1 start from 4V).
So in this Ideal scenario (Ideal means No Net Voltage Drop), to capture the Logic 0 at the input of Gate 2, Output voltage of Gate 1 for Logic 0 should have below condition.

V_OL ≤ V_IL

On the basic of above 2 scenarios, I can easily summarize that ...

V_OH ≥ V_IH
V_OL ≤ V_IL

In above example, we have discussed all between 2 different gates (Output logic of 1st Gate and Input Logic of 2nd) and you may be thinking on the basis we summarize this relationship (because original question was Input Logic Vs Output Logic of Same Gate :)). Just in case, if that’s your confusion – then check again – I have mentioned above that both gates are identical (so it means input logic levels of 2nd Gate == Input Logic Levels of 1st Gate also. :):) ).

On the basis of this, if anyone give you below 4 options and ask you which one is the right set of Input-Output Logic combination – I am sure , it will be easy to find out. (I am not going to give answer, you can write in comment section with reason :) ).

Till now, we considered the Ideal scenario (NO voltage drop across NET) But as you know nothing is ideal in this world, so keeping that in mind – our conditions changes and in real world condition will be ….

V_OH > V_IH
V_OL < V_IL

Now, If I want to represent this In a single diagram – below is the representation.

Okay, so till now we are able to understand different nomenclature, Like V_OH , V_IH , V_OL , V_IL in logic level, their importance and relationship between them.

Now, if you remember, our discussion started with 2 things – Undefined Region and Noise Margin...

Noise Region and Undefined Region

To understand the Noise Margin, you have to first understand what a "Noise" can do! In general, we can categorize Noise in 2 ways

• Noise Inside the Gate
• Noise inside the Gate already taken care during simulation of Gate & only after that we define (or conclude) V_OH, V_OL
• Noise Outside the Gate
• This Noise effects the signal which is traveling from the output pin of a gate to input pin to other gate

Let's talk about the Noise which developed or generated because of environment and effect Signal traveling between input and output pin of a Gate.

In general, Noise is Random in nature and you can’t model it exactly (at least the source of Noise :)). This Noise can be positive or negative in nature (when I am saying positive/negative it means with respect to zero reference level). It means if there is a output signal of 4V and suddenly a positive noise of 0.5V come, signal convert into 4.5V. Similarly, if Negative Noise of 0.5V come, output signal convert into 3.5V.

Let’s consider a scenario,

For Gate 2: V_OH = 4V, V_IH = 3.5V,
Output signal from the 1st Gate is of 4V.

Now, question is what should be the maximum Noise value (in terms of voltage), so that even after noise 2nd Gate identify Logic 1 correctly ?

As, we have discussed Noise can be Positive and Negative also –

If Noise is Positive then it’s going to add in output voltage .. Means output is going to increase above 4V, which is okay for 2nd gate because for 2nd Gate Voltage range start for Logic level 1 is above 3.5V.

If Noise is Negative then it’s going to reduce output voltage .. It means output is going to decrease & value will be less the 4V. If that’s the case we have to understand that Voltage range for Input logic High (1) start from 3.5V. Any signal less then 3.5V is not considered as Logic 1 signal at the input of Gate2. So, I can easily say that in this scenario, Maximum allowable Noise in negative side is 4V – 3.5V = 0.5V or you can say that V_OH – V_IH. This difference we are saying NOISE MARGIN for LOGIC HIGH.

NOISE MARGIN HIGH LOGIC = V_OH – V_IH

With the similar explanation, I can easily say that in case of Logic 0, any noise which increases the voltage of output logic signal beyond Max input Voltage for Logic 0, consider as not acceptable Noise. So, any Noise between V_OL and V_IL is acceptable for Logic 0. Means..

NOISE MARGIN LOW LOGIC = V_IL – V_OL

Okay, so if this is the NOISE Margin, what’s the Undefined Region ? Answer is simple – Remaining portion is considered as Undefined Region. :)

I know, now you may be thinking that above description is good when we talk in terms of Input Vs Output Logic Level. But If we talk only about Logic level (Individual), then how can we defined the region between “Min Voltage for Logic 1” and “Max Voltage for Logic 0”.

Any signal with in this range is considered as uncertain, and no one is going to give you guarantee how other Gate (input Gate) would interpret such signal because that depends on Input level of 2nd gate :). Now, if your other gate (gate which is going to receive this signal at input port) has wider voltage range for Logic 1 or 0, most of your signals between uncertain range can be consider either Logic 0 or Logic 1.

So, This region is considered as Uncertain Region. It means signal in this region can be consider as Logic 0 or 1 depends on Logic level Range of Next stage Input gate. I will not say that it’s Undefined Region because undefined means – It's neither be 0 nor 1.

Note: "Either be 0 or 1" is completely different from "Neither be 0 nor 1".

If you are not clear with my statement – let's try to understand with one more example of say scenario.:).

In above circuit, output of NAND Gate“1” is connected with 2 another NAND Gates. All NAND gates are different.

Input Logic Level of NAND 2:
Logic 0 – From 0V to 2V
Logic 1 – From 3V to 5V

Input Logic Level of NAND 3:
Logic 0 – From 0V to 1.5V
Logic 1 – From 3.5V to 5V.

Output Logic Level of NAND 1:
Logic 0 – From 0V to 1V
Logic 1 – From 4V to 5V.

Let’s assume At a particular instance, the output signal voltage at NAND Gate 1 is 3.2V. As per Output voltage levels (as per our above discussion), it’s in Uncertain Area. When this signal propagate through wire & reaches at

• NAND Gate 3
• It’s below Voltage range for Logic level 1 (3.5V to 5V)
• And above Voltage range for Logic level 0 (0V to 1.5V)
• So this signal is considered as part of UNDEFINED Region.
• NAND Gate 2
• It’s above Voltage range for Logic level 1 (3V to 5V)
• So, this signal is considered as part of Logic 1.

So, it means Same voltage can be part of Undefined Region and also as part of Logic Level 1. Same case can happen for Logic 0 also.

In Summary:

• Range between V_OH and V_OL can be consider as uncertain range with respect to that gate.
• A range between V_IH and V_IL is considered as undefined region for that particular gate.
• Undefined region is with respect to Input Signal range.
• Uncertain Region is with respect to Output Signal Logic Range
• Noise Margin always with respect to Input and Output Logic range. :)

V_OH > V_IH
V_OL < V_IL
NOISE MARGIN HIGH LOGIC = V_OH – V_IH
NOISE MARGIN LOW LOGIC = V_IL – V_OL

I hope this article will help you to understand the Logic Level concepts in much more depth and help everyone (Specially Students) to understand the concepts :).


HAPPY LEARNING