Metal Wire Orientation (HVH or VHV)

In previous articles, we have discussed a lot about type of metal wire like Mx, My and others. We have also discussed about the Metal stack like 6 Metal layer stack : M1_3Mx_My_Mz. (If you have confusion, please refer Article "Metal Layer Stack Nomenclature").

In this article, we are going to understand another important concept: "Metal layer Orientation". Actually during routing of design, we use a terminology "Preferred Routing Direction" of Metal layer. May be you have heard HVH or VHV routing strategy. Even if not - then I am sure you have seen below fig somewhere :) .

In the above pic, you can see that M1, M3 & M5 are in Horizontal direction and M2 & M4 are in vertical direction. Still confused ??? :) Let me help you.

Metal wires in our design are at different levels. If, I assume that M1 is at first level then M2 is at second level, M3 at third and so on. Type of Metal (Mx, My, Mz) depends as per Metal Stack you are going to choose for your design. (For more detailing about the Metal stack - please refer Article "Metal Layer Stack"). By now, you should be clear that different metals present at different height with respect to substrate.

Now, only one question is remaining, how we are going to route these metals? How in the sense - in which direction or say orientation. Is/are there any standard/s behind this or user can route these metals wires as per their requirement? Very short answer of this question - There are standards or say recommendation for routing Metal wires. Timing is very critical now a days. From metal wires point of view - capacitance between them plays a very important role. (Note: Delay has relationship with RC constant - and this C is because of Capacitance between the wires). So as a designer we have to understand or say use those technique which can minimize these unwanted Capacitance (Remember - capacitance between Wires are always unwanted. It's always has side effect in negative sense :) ). To understand different type of capacitance between wires, you can refer Article "Basic of Capacitance & Resistance (from VLSI Point of view)"

Capacitance between 2 plates depends on area of plates parallel to each other OR I can say overlap area between 2 metal wires. During Routing - there are 2 extreme routing methodology.

1. Parallel Routing Grid
2. Cross Routing Grid

If we place metal wire on these routing grids (as an example - just picked only 2 wires of same metal layer), you can easily understand the concept of overlap area. Remember, right now we are talking about Ground cap (or Area cap) and not Coupling cap.

Parallel Metal Wire Orientation:

In the below figure, I have tried to show arrangement of capacitance between parallel metal wire between metal layers of different levels Like capacitance between M1 and M2. Since M1 and M2 both are parallel to each other 100%, Capacitance between them has dependency on width and length of the wire. This arrangement gives maximum Ground cap (Area cap).
Note: We are not discussing the capacitance between same type of metal layers (Between M1 and M1) known as Coupling Capacitance.

Cross / Perpendicular Metal Wire Orientation:

In the below figure, you can see that overlap area between M1 and M2 is only at their cross-section. This overlap area depends on their corresponding width parameter. You can see that their is no dependency on length of the wire. This arrangement gives minimum Ground cap (Area cap).
Front view and Side view of this arrangement helps you to understand this routing methodology more closely.

You can see that if we want to reduce the CAP then orientation of the Metal wire is very important. Cross (perpendicular) metal wire orientation gives minimum capacitance and that's the reason it's recommended. One of the direction is considered as Horizontal and other as Vertical. That's the reason - these orientation is known as HVH or VHV orientation (and corresponding routing strategy as HVH or VHV routing methods).

Delay Interview Questions (Part 2)

In the last part (Delay Interview Questions: Part 1), we have discusses 2 scenarios

1. Min & Max Delay Between 2 points having multi-paths when Delay are given as absolute number.
2. Min & Max Delay between 2 points having multi-paths when Delay are given as Rise and Fall delay.

We have discussed these concepts from Interview point of view.
Note: Example 1 and Example 2, we have already discussed in last article.

Example 3:

Note: Above figure is same as in Example 1 and Example 2 (with small addition).

All Buffer has same (min, max) delay = (0.1ns, 0.2ns)
All NOT Gate has same (min, max) delay = (0.25ns, 1ns)
AND gate (min, max) delay:
                  Arc a1 -> y1 = (1.25ns, 1.5ns)
                  Arc b1 -> y1 = (1.1ns, 1.9ns)
OR gate (min, max) delay:
                  Arc a2 -> y2 = (0.3ns, 0.4ns)
                  Arc b2 -> y2 = (0.5ns, 0.9ns)

Question: Find out the Minimum and Maximum Delay between Q1 and D2?

Explanation:
This question is almost equal to the example 1 but with slight modification. Now, we are talking about the different input and output combination of AND gate. Remember, every input and output combination has it's own delay value. When we talk about the Delay of a Gate and if it's not related to input and output combination, it means we are talking about Boundaries of overall gate delay. To understand this concept - you need to revise or say understand Timing Arc concepts. Please read article Timing Arc and Unate: Timing Arc.

Intension of this question is to get more accurate delay value based on Path base analysis.
Note: Delay calculation in such circuit are of 2 type - Path base Analysis and Graph Base Analysis. You can get more detail about this in Article - Path Base Vs Graph Base Analysis: Part 1.

There is a little bit change in the picture of Path 1 and Path 2 (in compare to Example 1 and Example 2).

In the above figure, you can see that
Path 1: Q1 -> Inverter -> b1 -> y1 -> Buffer -> a2 -> y2 -> Buffer -> D2
Path 2: Q1 -> Inverter -> Inverter -> Inverter -> b2 -> y2 -> Buffer -> D2

In Path 1:
b1 -> y1 is basically part of AND gate and during delay calculation we will use delay value as per Arc b1 -> y1 = (1.1ns, 1.9ns).
a2 - > y2 is basically part of OR gate and delay values are as per Arc a2 -> y2 = (0.3ns, 0.4ns).

In Path 2:
b2 - > y2 is basically part of OR gate and delay values are as per Arc b2 -> y2 = (0.5ns, 0.9ns).

Solution:
Path 1 (Min Delay) : 0.25 (inverter) + 1.1 (b1 -> y1) + 0.1 (buffer) + 0.3 (a2 -> y2) + 0.1 (buffer) = 1.85ns
Path 1 (Max Delay) : 1.00 (inverter) + 1.9 (b1 -> y1) + 0.2 (buffer) + 0.4 (a2 -> y2) + 0.2 (buffer) = 3.70ns

Path 2 (Min Delay) : 0.25 (inverter) + 0.25 (inverter) + 0.25 (inverter) + 0.5 (b2 -> y2) + 0.1 (buffer) = 1.35ns
Path 2 (Max Delay) : 1.00 (inverter) + 1.0 (inverter) + 1.0 (inverter) + 0.9 (b2 -> y2) + 0.2 (buffer) = 4.1ns

Overall Min Delay between Q1 and D2 = 1.35ns (From Path 2)
Overall Max Delay between Q1 and D2 = 4.1ns (From Path 2)

Example 4:

All Buffer has same delay:
                  Tphl (min, max) = (0.1ns, 0.18ns)
                  Tplh (min, max) = (0.15ns, 0.20ns)
All NOT Gate has same delay:
                  Tphl (min, max) = (0.25ns, 0.75ns)
                  Tplh (min, max) = (0.5ns, 1.0ns)
AND gate delay:
        Arc a1 -> y1:
                    Tphl (min, max) = (1.25ns, 1.5ns)
                    Tplh (min, max) = (1.3ns, 1.75ns)
        Arc b1 -> y1
                    Tphl (min, max) = (1.0ns, 1.9ns)
                    Tplh (min, max) = (1.1ns, 2.0ns)
OR gate (min, max) delay:
        Arc a2 -> y2:
                    Tphl (min, max) = (0.3ns, 0.35ns)
                    Tplh (min, max) = (0.31ns, 0.4ns)
        Arc b2 -> y2:
                    Tphl (min, max) = (0.51ns, 0.9ns)
                    Tplh (min, max) = (0.5ns, 0.75ns)

Note:
Tphl = Propagation Delay High to Low
Tplh = Propagation Delay Low to High

Question: Find out the Tplh and Tphl at point D2 with respect to Input Q1?

Explanation:
For this you need to understand the concepts of Tphl and Tplh. I am assuming that you know this part. Here we have to understand how different waveform (Rising input or Falling input) is going to behave in this circuit.

There is a little bit change in the picture of Path 1 and Path 2 (in compare to Example 1 and Example 2).

We have to do 2 type of analysis for each path - Rising & Falling signal analysis at D1 for both paths.

Rising Signal Analysis (For Path1):

• Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
• AND gate is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of AND gate for ARC b1 -> y1 => (1.0ns, 1.9ns)
• Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of Buffer gate => (0.1ns, 0.18ns)
• OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of OR gate for ARC a2 -> y2 => (0.3ns, 0.35ns)
• Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of Buffer gate => (0.1ns, 0.18ns)

For Rising Signal at the Input (Q1), we are getting Falling Signal at the Output (D2) through Path1. So in this scenario, delay between Q1 and D1 through Path1 = Tphl.
Minimum Tphl at D1 through Path 1 = 0.25ns + 1.0ns + 0.1ns + 0.3ns + 0.1ns = 1.75ns
Maximum Tphl at D1 through Path 1 = 0.75ns + 1.9ns + 0.18ns + 0.35ns + 0.18ns = 3.36ns

Falling Signal Analysis (For Path1):

• Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
• AND gate is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of AND gate for ARC b1 -> y1 => (1.1ns, 2.0ns)
• Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of Buffer gate => (0.15ns, 0.20ns)
• OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of OR gate for ARC a2 -> y2 => (0.31ns, 0.4ns)
• Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of Buffer gate => (0.15ns, 0.20ns)

For Falling Signal at the Input (Q1), we are getting Rising Signal at the Output (D2) through Path1. So in this scenario, delay between Q1 and D1 through Path1 = Tplh.
Minimum Tplh at D1 through Path 1 = 0.5ns + 1.1ns + 0.15ns + 0.31ns + 0.15ns = 2.21ns
Maximum Tplh at D1 through Path 1 = 1.0ns + 2.0ns + 0.20ns + 0.40ns + 0.20ns = 3.80ns

Rising Signal Analysis (For Path2):

• Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
• Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
• Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
• OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of OR gate for ARC b2 -> y2 => (0.51ns, 0.9ns)
• Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of Buffer gate => (0.1ns, 0.18ns)

For Rising Signal at the Input (Q1), we are getting Falling Signal at the Output (D2) through Path2. So in this scenario, delay between Q1 and D1 through Path2 = Tphl.
Minimum Tphl at D1 through Path 2 = 0.25ns + 0.5ns + 0.25ns + 0.51ns + 0.10ns = 1.61ns
Maximum Tphl at D1 through Path 2 = 0.75ns + 1.0ns + 0.75ns + 0.90ns + 0.18ns = 3.58ns

Falling Signal Analysis (For Path2):

• Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
• Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
• Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
• OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of OR gate for ARC b2 -> y2 => (0.5ns, 0.75ns)
• Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of Buffer gate => (0.15ns, 0.20ns)

For Falling Signal at the Input (Q1), we are getting Rising Signal at the Output (D2) through Path2. So in this scenario, delay between Q1 and D1 through Path2 = Tplh.
Minimum Tplh at D1 through Path 2 = 0.50ns + 0.25ns + 0.50ns + 0.50ns + 0.15ns = 1.90ns
Maximum Tplh at D1 through Path 2 = 1.00ns + 0.75ns + 1.00ns + 0.75ns + 0.20ns = 3.70ns

Solution:
Through Path 1 (Min Tplh) : 2.21ns
Through Path 1 (Min Tphl) : 1.75ns

Through Path 2 (Min Tplh) : 1.90ns
Through Path 2 (Min Tphl) : 1.61ns

Through Path 1 (Max Tplh) : 3.80ns
Through Path 1 (Max Tphl) : 3.36ns

Through Path 2 (Max Tplh) : 3.70ns
Through Path 2 (Max Tphl) : 3.58ns

Overall Minimum Tplh at D2 (when input is at Q1) = 1.90ns (Through Path 2)
Overall Maximum Tplh at D2 (when input is at Q1) = 3.80ns (Through Path 1)
Overall Minimum Tphl at D2 (when input is at Q1) = 1.61ns (Through Path 2)
Overall Maximum Tphl at D2 (when input is at Q1) = 3.58ns (Through Path 2)

In Summary, I can write, At D2 with respect to Q1 Tphl = (1.61ns, 3.58ns) & Tplh = (1.90ns, 3.80ns)

Is it done? I mean do you think Interviewer is going to stop at this point. :) :) Don't ever think. By now they will realize that you are good in below concepts.

• Min and Max Delay Calculation
• Delay calculation based on Timing Arc (I can say some part of Path base & Graph base analysis)
• Tphl and Tplh based Delay Calculation
• Multipath Delay Calculation
• Use of Rising edge and Falling Edge at Input during delay calculation

Now, it's time to check few more concepts related to CELL Delay (Like Cell Delay as a function of Input Transition Vs Output Load) and then how you can use those concepts in delay calculation of Combinational Circuit. :) Lets discuss this in Next Article.

Path Base Analysis (PBA) Vs Graph Base Analysis (GBA) - part1

Today, we are going to discuss about the Path base analysis Vs Graph base analysis. As such difference is more complex compare to what I am going to explain, but right now it's sufficient to start with. :)

Let's you have a combinational path with Net delay (min, max) and Cell delay (As per the Timing Arc). If, you have any confusion with respect to the timing arc, please refer below articles.

• Introduction of Timing Arc
• Unateness

In the below figure, you can see AND gate (1) has 2 input, so 2 set of input-output delay combination.

• Min Delay = 0.5ns, Max Delay = 1.5ns
• Min Delay = 0.2ns, Max Delay = 1.2ns

Similarly, for other logic gates.

Now, if I will ask you to calculate the delay between point A and point B, then the concept of PBA and GBA comes into the picture. Before, I explain you this concept, please refer below few figures and then see the difference between PBA and GBA.

I am sure, if you have notice closely, then you have already realized the difference. :) But still let me highlight that.

In GBA (Graph Base Analysis), in place of choosing 2 combinations of AND gate (1) delay, i.e. (Combination_1: 0.5ns, 1.5ns ; Combination_2: 0.2ns, 1.2ns) we choose extreme boundaries, i.e. min delay = 0.2ns and max delay = 1.5ns.

In case of PBA (Path base Analysis), we are using actual delay between input pin and output combination (means choosing both combination of delay).

• Combination_1: 0.5ns, 1.5ns
• Combination_2: 0.2ns, 1.2ns

Note: Check the similar difference for AND gate (2) also.

You might be thinking that this is not accurate (means why in GBA we missed 2 value), we are adding unnecessary delay in our calculation. And I am glad to say that you are right. :) The reason we are doing this because from tool point of view - doing analysis or say calculation as per GBA is very fast compare to PBA. Runtime of tool is very low. And only difference is that we are adding pessimism in our calculation.

Now, if you want to understand the calculation of delay between different input pin (A, B, C) and Output Pin (Y), please check below figures.

Note: For clarity purpose (used different color combination) - I did this calculation and pasting in the form of picture. :)

Delay Calculation in Case of GBA (Graph base Analysis).

Delay Calculation in Case of PBA (Path base Analysis).

Important observation, which you all should noticed:

Delay between A and Y
Graph base analysis (Min, Max) : 7.25ns, 10.35ns
Path base analysis (Min, Max) : 7.55ns, 10.10ns

You can see that delay between A and Y - in case of GBA is superset of PBA.
Means:
min_delay_in_GBA < min_delay_in_PBA
max_delay_in_GBA > max_delay_in_PBA

Delay between B and Y
Graph base analysis (Min, Max) : 7.75ns, 10.85ns
Path base analysis (Min, Max) : 7.75ns, 10.30ns

You can see that delay between B and Y - in case of GBA is superset of PBA.
Means:
min_delay_in_GBA = min_delay_in_PBA
max_delay_in_GBA > max_delay_in_PBA


Delay between C and Y
Graph base analysis (Min, Max) : 7.05ns, 9.05ns
Path base analysis (Min, Max) : 7.25ns, 9.05ns

You can see that delay between A and Y - in case of GBA is superset of PBA.
Means:
min_delay_in_GBA < min_delay_in_PBA
max_delay_in_GBA = max_delay_in_PBA

Let me summarize whole concept:

min_delay_in_GBA <= min_delay_in_PBA
max_delay_in_GBA >= max_delay_in_PBA

Now, everything is good but still you may have confusion or question - why GBA? Because from above calculation, it's not clear how it's going to save Analysis Time of a Tool. How it's beneficial for Industry? If you have all these questions, no need to worry, I will explain but not in this article. I will do that next time. But I can give you hint, so that you can think about this once.
Hint:
1) Check how these minimum and maximum delays are calculated?
2) Adding Pessimism is not an problem, it's just margin in your delay calculation. How adding margin can help us?
3) What all different environment or other factors or parameters you have to consider while calculating Delay based on different timing Arc of a gate?

I think, for now, these hints are good enough. Comment here - if you know the Answer of this, else wait for next related article. :)


BEST OF LUCK.
By - Puneet Mittal
(Founder of VLSI-Expert Group)PBA)