UNATE : Timing Arc

STA & SI:: Chapter 1: Introduction
	1.1a	1.1b	1.1c	1.2a	1.2b
INTRODUCTION	Timing Arc	Unate: Timing Arc	Unateness of Complex Circuit: Timing Arc	LIB File syntax for Logic Gates: Timing Sense	LIB File syntax for Complex Circuit: Timing Sense

Previous Article is all about "What is Timing Arc?" and "How can you categorize them (Net Arc and Gate Arc; Delay Arc and Constraint Arc)?"
But still we need to understand how timing arc helps us to answer our questions related to any Standard Cell or any Flip-flop or any system (like Macros, IPs)...

1. For a Particular Input (Rising or falling), what type of Output (output is rising or falling or no change) you get ?
2. How much time (may be in the form of Delay) it will take to respond for a particular Input ?
3. Is there any constraint on any pin and if yes, then what are those and on what pin ?

First Question can be answered if we know: How Input pin is logically connected with Output pin!

What is the meaning of Logically connection? It Means, what is going to happen “For Rising Input"...whether Output

• Fall or
• Rise or
• No Change

Timing Arc help us to identify this with a property known as Unate.

UNATE

Unate are of three types:

• Positive Unate:
• Rising Input – Rising Output OR No change in Output.
• If we apply Rising signal to the input of a Timing Arc, corresponding output signal is either Rising or there is "No change".
• Falling Input – Falling Output OR No change in Output
• If we apply Faling signal to the input of a Timing Arc, corresponding output signal is either Falling or there is "No change".
• E.g:
• BUFFER
• AND gate (will explain this in detail later below)
• OR gate (will explain this in detail later below)
• Negative Unate:
• Rising Input – Falling Output or No change in Output.
• If we apply rising signal to the input of a Timing Arc, corresponding output signal is either Falling or there is "No change".
• Falling Input – Rising Output or No change in Output
• If we apply Falling signal to the input of a Timing Arc, corresponding output signal is either Rising or there is "No change".
• E.g:
• Inverter (NOT gate)
• NAND gate (will explain this in detail later)
• NOR gate (will explain this in detail later)
• Non_Unate:
• The non-unate represents a function where change in output value cannot be determined from the direction of the change in the input value. Output pin value is not dependent on single Input Pin. It also depends on 2nd Input pin. Since Timing arc will be between the Single Input and Single Output pin, so it’s difficult to identify this relationship directly.
• E.g:
• XOR gate (will explain this in detail later)
• XNOR gate (will explain this in detail later)

Buffer:

In the Buffer there is one input pin and one output pin. We all know the Behavior of BUFFER gate as:-

• Rising Input results Rising Output.
• Falling Input results Falling Output.

So, Timing Arc between Input and Output pin of Buffer are Positive Unate.

Remember, there are 2 Timing arcs in Buffer: One for Rising Edge and other for Falling edge.

Inverter:

In the NOT Gate (Inverter) there is one input pin and one output pin. Behavior of Inverter also we know very well.

• Rising Input results Falling Output.
• Falling Input results Rising Output.

So, Timing Arc between Input and Output pin of Inverter are Negative Unate.

Remember, there are 2 Timing arcs in Inverter: One for Rising Edge and other for Falling edge.

AND Gate:

Above is the "Truth Table" of AND gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - No change (constant at 0)
A = 1 , B (0-> 1) ; Y - Changes from 0-> 1

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - No change (constant at 0)
B = 1 , A (0-> 1) ; Y - Changes from 0-> 1

In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - No change (constant at 0)
A = 1 , B (1-> 0) ; Y - Change from 1-> 0
B = 0 , A (1-> 0) ; Y - No change (constant at 0)
B = 1 , A (1-> 0) ; Y - Change from 1-> 0

So, in both the cases - Timing arc between A-Y and B-Y is Positive Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in AND gate:

1. Input Pin A to Output Pin Y for Rising Edge
2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

OR Gate:

Above is the "Truth Table" of OR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 0-> 1
A = 1 , B (0-> 1) ; Y - No change (constant at 1)

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 0-> 1
B = 1 , A (0-> 1) ; Y - No change (constant at 1)

In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 1-> 0
A = 1 , B (1-> 0) ; Y - No change (constant at 1)
B = 0 , A (1-> 0) ; Y - Change from 1-> 0
B = 1 , A (1-> 0) ; Y - No change (constant at 1)

So, in both the cases - Timing arc between A-Y and B-Y is Positive Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in OR gate:

1. Input Pin A to Output Pin Y for Rising Edge
2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

NAND Gate:

Above is the "Truth Table" of NAND gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - No change (constant at 1)
A = 1 , B (0-> 1) ; Y - Changes from 1-> 0

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - No change (constant at 1)
B = 1 , A (0-> 1) ; Y - Changes from 1-> 0

In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - No change (constant at 1)
A = 1 , B (1-> 0) ; Y - Change from 0-> 1
B = 0 , A (1-> 0) ; Y - No change (constant at 1)
B = 1 , A (1-> 0) ; Y - Change from 0-> 1

So, in both the cases - Timing arc between A-Y and B-Y is Negative Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in NAND gate:

1. Input Pin A to Output Pin Y for Rising Edge
2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

NOR Gate:

Above is the "Truth Table" of NOR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 1-> 0
A = 1 , B (0-> 1) ; Y - No change (constant at 0)

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 1-> 0
B = 1 , A (0-> 1) ; Y - No change (constant at 0)

In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 0-> 1
A = 1 , B (1-> 0) ; Y - No change (constant at 0)
B = 0 , A (1-> 0) ; Y - Change from 0-> 1
B = 1 , A (1-> 0) ; Y - No change (constant at 0)

So, in both the cases - Timing arc between A-Y and B-Y is Negative Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in NOR gate:

1. Input Pin A to Output Pin Y for Rising Edge
2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

XOR Gate:

Above is the "Truth Table" of XOR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 0-> 1
A = 1 , B (0-> 1) ; Y - Changes from 1-> 0

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 0-> 1
B = 1 , A (0-> 1) ; Y - Changes from 1-> 0

In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 1-> 0
A = 1 , B (1-> 0) ; Y - Change from 0-> 1
B = 0 , A (1-> 0) ; Y - Change from 1-> 0
B = 1 , A (1-> 0) ; Y - Change from 0-> 1

This one is a bit different from other gates (which we have reviewed till now).
You can see that change in the output can't be decided just by seeing/observing one input pin. For B changes from '0' to '1', output can change from '1' to '0' or '0' to '1' depends on the value at A. In other way, I can say that change in the output don't have any pre-defined pattern with respect to Pin B or Pin A indivisibly. It depends on collective behavior of A and B.
Such type of Timing Arcs neither fall in the category of positive_unate nor in negative_unate. These Timing Arcs are Non_Unate.

Timing arc between A-Y and B-Y is Non Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in XOR gate:

1. Input Pin A to Output Pin Y for Rising Edge
2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

XNOR Gate:

Above is the "Truth Table" of XNOR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 1-> 0
A = 1 , B (0-> 1) ; Y - Changes from 0-> 1

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 1-> 0
B = 1 , A (0-> 1) ; Y - Changes from 0-> 1

In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 0-> 1
A = 1 , B (1-> 0) ; Y - Change from 1-> 0
B = 0 , A (1-> 0) ; Y - Change from 0-> 1
B = 1 , A (1-> 0) ; Y - Change from 1-> 0

Explanation is same as in case of XOR gate - copy paste the same paragraph here :).
You can see that change in the output can't be decided just by seeing/observing one input pin. For B changes from '0' to '1', output can change from '1' to '0' or '0' to '1' depends on the value at A. In other way, I can say that change in the output don't have any pre-defined pattern with respect to Pin B or Pin A indivisibly. It depends on collective behavior of A and B.
Such type of Timing Arcs neither fall in the category of positive_unate nor in negative_unate. These Timing Arcs are Non_Unate.

Timing arc between A-Y and B-Y is Non Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in XNOR gate:

1. Input Pin A to Output Pin Y for Rising Edge
2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

I am sure, by now, you have developed or revised the concept of Unate in Timing Arc. With the help of Truth table, you can easily figure out the Unateness of any Timing arc. Even If you are going to design any circuit or system (which is not in the list of Standard gates), then you can yourself figure out the Unateness property of different Timing arcs in that system.

We will discuss about that in more detail in next few articles. Like how these (Timing Arc , Unateness ) represent in Timing Library, how different values are captured in Timing Library and a lot about the Timing Arcs. :)

Interview Questions

I have tried to capture few Interview questions here which can help you big time during your preparation.

1. What are the different types of Timing Arc ?
2. What is Unateness of a Timing Arc ?
3. What do you mean by Positive_unate of a Timing Arc?
4. What do you mean by Negative_unate of a Timing Arc?
5. What is the difference between Non-unate Timing arc and Positive Timing Arc ?
6. How many Timing Arcs are present in case of Buffer?
7. How many Timing Arcs are present in a 2 input NAND gate?
8. How to represent Timing Arcs in the Timing Library ?
9. A timing arc is positive Unate, if we apply rising edge at the input of the Timing arc, corresponding output will change or not ?
10. How many Timing arcs are present for a 3 input XOR gate?
11. What's the Unateness of different Timing Arc for a 3 input XNOR gate ?

The newly launched product "Static Timing Analysis (STA) Papers" by VLSI Expert Pvt. Ltd., can help you in preparing for Interview & written test. These papers are designed after having discussion with by Industry people.

5 Steps to Crack VLSI Interview

"5 Steps to Crack VLSI Interview"... Sounds Good :) But before I share with you these Steps, you should know how I have figured out these 5 Steps.
I am in touch with several Industry experts (Technical and Non-Technical Managers), Recruiters (HR people), Universities, Colleges, Professors, Training and Placements Officers (TPO) and Last but not least "Students".
In the last couple of years, I had rounds of very intensive discussions with all of these and after that I have come across major challenges faced by the Students (In the hiring process) and challenges faced by Industry people in recruiting the right VLSI candidates. I will discuss those in detail later on but for today it's important to know "How to break the ICE" :)

Step 1: Evaluate Semiconductor Industry.

When I say evaluate Industry, mean to consider several parameters, which can help you to understand: Are you on right path or not ?

Parameter 1: Is this right Industry for you?
First, you should know why you want to enter in this Industry. If it's because of following reasons then you are on the wrong path.
(Read My previous Article for details. 5 Reason VLSI Industry Not For you)

1. Want "Huge Money in Short Time"
2. Are "Not passionate about Electronics"
3. Want to "Sit back and Relax in Long Run"
4. Want to "Start your Own business with Zero Investment"
5. Are "Not Interested In Coding and Automation"

Parameter 2: How Much you know about VLSI/Semiconductor Industry?
This is again a very important parameter before we think about the Semiconductor Industry. Most of the time students apply for VLSI jobs even don't know too much profile, requirements and many other things. During my conversations with Industry experts, this comes out to be an important reason, why they show reluctance to hire a fresher. (Read More : Why VLSI Industry Reluctance to Hire Fresher??)
I have following suggestions for students aspiring career in VLSI Industry:

1. Increase your knowledge base about the VLSI Industry
• Read Blogs/ Articles/ Magazines
• Talk to your Seniors / Friends / Relatives to know more about VLSI Industry
• Attend Seminars / Conferences which are specific to Semiconductor Industry
• Like, Subscribe, Join different Groups / Community
2. Put more effort to fill your knowledge gap
• Read different books and always try to understand the roots of different concepts
• If possible, attend different Courses/ Training programs / Workshops

Step 2: Evaluate yourself.

This is something which is required big time whenever you do preparation for anything either it's any competitive exams or Interview or Semesters Exams. You can find a lot of material or instruments/tools which can help you to evaluate your preparation for the competitive exams. Similarly, Internal sessional exams helps you to evaluate for the Semester's exams. But we don't have any mechanism for Self evaluation for Interview or Written Test.
After discussion with Students, I have figured out that it's a big time in demand. Every student is looking for following things:

• Interview Questions: You can find these over Internet but the point is who captured those questions, Industry people or a Candidate (also similar to you)
• Solutions or Answer of several Questions: Even if there are good number of questions available, what about their solutions or answers. Are these solutions as per Industry expectations?
• Follow-up questions: Even if you have questions but are they composed as per Interview pattern? Interview pattern is very much different from the normal exam. (Read More: Interview Pattern Vs Written-Test Pattern)

Check one of my book for VLSI Interview Questions: Static Timing Analysis. It's a Kindle edition.
VLSI INTERVIEW QUESTION: Static Timing analysis : Puneet Mittal (Author)
VLSI INTERVIEW QUESTION: Static Timing analysis : Puneet Mittal (Author) : (In INR)

Now even if someone gives all these details, we will still be in doubt about...

• What if Interviewer asks something else?
• What if I am not able to perform well?
• How can I assure that I am ready for the Interview?

These questions can be solved when you go through a system which can help you in Evaluation/Assessment.

"No one can win all the time. But you have got to learn from all you do - Both Successes and Failures. Always do a Self assessment."

By - Michael Sachs

Whole purpose of evaluation should be to categorise different topics in strong Vs weak basket. In the process of Self Evaluation - the most important thing is to know - where we stand right now. What are the weak and strong areas. If someone help us to find this part then we can easily fix rest of the things (More discussion on this in Step 4).

Step 3: Follow a simple and proven study pattern

When I interacted with students and I asked them about their study pattern, like how do you start preparing for VLSI Interview? Students shared that they start with the advance concepts and what do they do if they get stuck somewhere...the response was, we go back and clear (brush up) those concepts. But according to me, this approach is very complex and timing consuming. Check this picture.

If you jump to the Level 4 directly, then there are equal chances to fall back or say it will take time to understand these concepts or may be you have to come back to level 3 to brush up linked concepts and then again you go back to level 4. Still if something is missing on fundamental side, there is equal possibility that you have to go back to level 2 and then level 4. This iteration can be "N" number of times. Basically you do not realize that there is big iteration or time spend in the whole process.

Now, if someone tell you the study pattern with 100% success rate, then will it be good for you. Like during college – we have semester 1 and followed by semester 2 and so on. Every Semester has predefined syllabi by experts so that you learn fast and don’t loose interest.
Similarly, while preparing for any competitive exam or preparing for an Interview – we should follow a Systematic approach as well, in terms of study pattern.

• Like what to study?
• Which topic to read first ? Which is the next topic in sequence ?
• When to Study?
• What should be the Weightage of a certain topic and so on.

This pattern is very simple and also proven by experts. Check below figure.

This pattern also has some catches. That's the Part of Next Step. :)

Step 4: Focus on Weak area and that's too as per required Weightage in Interview

There are Students who usually follow the simple and proven study pattern. But still they miss few things and get stuck at first level itself, unable to move forward.
Now imagine, you have started preparing for VLSI interview and decided to start from level 1 (In above diagram it's Number System). After a few days, your Semester exams come or some personal issue or something else which forced you to focus there for next few days. Now these few days convert into month and then you realized that you have to restart. Restart means - restart from the Number System :) because that's the simple and proven approach :). Oh My God once again the same thing. If this thing happens 2-3 times, you loose patience and you may jump to a complex approach :) :)

This happens because we don't know how to move forward in the proven approach itself. The Simple process should be

1. Evaluate yourself for a certain topic
2. Identify your Weak and Strong areas
3. Focus on your Weak area only and then move to next topic
4. Repeat the process from 1 to 3

In this way, you will not spend your time on your strong area and day by day you will strengthen your weak areas only.

When I say different topics, we need to understand that different topics have different weightage in the Interview process or say as per Industry requirements. I mean to say that in Semiconductor Industry, if we give same amount of time to Number System and Sequential Circuits, it's not justified (even though there are equal concepts to study in both topics). We should also need to know what's required and how much it is required. And as per that only we should divide our time in brushing up different concepts.

List of required Topics/ Concepts can be easily made using Google :) but weightage is not readily available to us from anywhere.

I have captured different questions of different topics for everyone. Check those one and see if that can help you.

Free Papers (You have to just enroll)

• STA (Static Timing Analysis papers)
• Unix/Linux papers
• System Verilog papers
• Verilog papers

Paid Papers (You can wait for offers :))

• STA (Static Timing Analysis)
• ASIC Verification (Verilog/SV)
• Unix and Scripting

Step 5: Profile / Resume Building and Developing soft skills

When I am talking about the Profile building, most of the time students miss a lot of important things. Different Industries need a different type of Resume since they have different requirements. Now if you want to enter in a Semiconductor industry but in your profile you will mention Java, .Net and similar topics, it's not going to help you. It's very important to mention right set of skills in your profile.

Apart from this, Semiconductor industry is very demanding and industry people are too busy. They don't want to spend lot of time with your profile to understand you (knowing that there are lot of other candidates with better written profile :) ). Your profile should be structured in such a way that information can be extracted very easily and as per other's requirement.

There are 3 Major sub-steps of screening based on your profile itself.

1. Screening by HR or Consultancy Firm: This one is highly focused on the keywords in your Profile. These keywords should be very well placed in such a way that it's automatically highlighted.
2. Screening by Technical Manager or Leader: This screening is very fast if different sections are placed in a proper manner. There is no standard way for this but if you have divided your profile in sections properly, that reflects your presentation skill.
3. Telephonic Screening: Sometime telephonic screening happen just to understand the profile. It can be 15-20 mins short process or 45-60 mins long process. Your clear thoughts and in sync with the profile is very important thing here. If you explain something which is not mentioned in your profile, then it becomes difficult for an Interviewer to understand your profile. Here, I recommend to build your profile on your own, don't ask or copy someone else profile :)

To know more about Resume building refer article: How to prepare Good Resume
For the Interview process or pattern, recommend you to refer Face to Face Interview Pattern.

I am sure above mentioned 5 steps help everyone. In case of any query, feel free to drop me a mail or comment.