Setup and Hold Violation: Advance STA (Static Timing Analysis )

Why, Setup Depends On Max Data path Delay and Hold Depends on Min Data Path Delay ?

Let me start with the important points those were the outcome of previous Article...

1. Setup and Hold Check is associated with the Capture Flip Flop and Capture Clock Edge.
2. Setup and Hold Time Create a window across the Capture Flip Flop and for proper operation of Flip flop, Data should be stable during that window.
3. Data launched by "Launch FF" (FF1) at clock edge "1" is going to capture by "Capture FF" (FF2) at clock edge "2" (Means Next clock Edge).
4. If data reach D2 pin of FF2 with in Setup time window of Next Clock Edge, That is consider a Setup Time Violation. In below figure, if the time when B reaches D2 lies in Gray area across edge "3" (or the time when A reaches D2 lies in Gray area across edge "2"), it's a Setup Violation for Timing path "Path1".
5. If data reach D2 pin of FF2 with in the Hold time window of Same Clock Edge, That is consider a Hold Time Violation. In the below figure, if the time when B reaches D2 lies in Red Brown area across edge "2", it's a hold Violation for Timing path "Path1".
6. Remember - If "B" reaches Red brown area across edge "2", it will unstable Data "A" And as per the Hold requirement - A should be stable in the Red brown area across edge "2".
7. From the above 3 points (#4,#5,#6), it's clear that Data "B" has a window between Two clock edge ("2" and "3") in which if it reach D2 pin of FF2, there will be no Setup and Hold Violation. And this is our requirement.

Now, you can easily say that data "B" will take a certain time to reach from Q1 to D2, you will calculate that part and you can easily figure out whether "B" is in Gray area (across "3") or Red Brown Area (across "2"). Once you know this information, it's very easy to fix setup and hold Violation. Then Why do People always so much worry about this ? Why, Fixing Setup and Hold Violation is so complex?

Whatever you are saying is 100% correct but you have added a certainty in above approach ("B" will take a certain time to reach from Q1 to D2). This certainty has a lot of hidden conditions.

You can understand this in the way - if someone ask you - How much time you will take to reach from location "X" to Location "Y" ? And you have to give specific numbers. I am sure you will answer something like this (I took some random numbers for clear understanding).

• It will take 60min to reach if I am driving a Car with a constant speed of 50miles/Hr and No Traffic Signal Stops me.
• It will take 65min to reach if I get all the Traffic Signal RED.
• It can be faster( near about 45min), if I ask My driver to drive my Car.
• In case of Peak Hr, there will be a lot of Traffic on road and during that time, It will take approx. 90min. And it doesn't matter whoever drive

I am sure you got my point. :) Now from Data point of view, If I will ask you same question once again "How much time Data "B" will take to reach D2 pin from Q1 pin ?" :) :)
Now, your answer will be some thing like this (if not - means you didn't get my point in above example :) :) ).

• It depends on previous data and current data. Means whether Data switches from 0->1, 0->0, 1->0 or 1->1.
• It depends on What type of Cell are we using ?
• It depends What's the environment condition? Is there anything which can change the Delay of the Path ?
• It depends if Path is fabricated as per your specification (no manufacturing defects).
• It depends on which PVT conditions we are calculating the delay?

So basically, you will come up with a lot of conditions and you will ask back a lot of questions before calculating and providing a specific value. There may be few questions which I can answer with definite numbers but lot of answer will be in a range. Like (my answer may be something like this)

• Environment temperature can vary between -40deg to 120deg.
• There will be only 2 type of transition between the Data in this path (0->1 and 1->0).
• We will use only LVT cells but that can be of any driving strength.
• I can't give you the guarantee that there will be no Manufacturing Defects, but yes foundry provided a "range" of data to model those defects.
• We have figured out 10 PVT corners for which this timing path should work without any violation.

So what's does it mean -Even, I have all the Answer but every thing is in range. Because I don't know who will be the end use?, in which environment condition this chip is going to use (Timing path belongs to whatever chip)?, What will be the condition of chip after 2 year?, During the manufacturing whether it will be in the middle of the wafer or at the edges? I myself have a lot of uncertainty in my answer.
As inputs are in range - you will calculate the delay (Time take by "B" to reach Q1 to D2) using all the combination and I can bet that you answer will be in a range not a certain value. :) :)

By now, you should be clear - why in real world we don't talk about the specific numbers. :):)

So it means "B" has a min and max time to reach D2 pin.
Min value means - as per the different combination of Input, "B" will not reach D2 pin before this minimum value.
Max value means - as per the different combination of Input, "B" will not reach D2 pin after this maximum value.

So now lets revisit the Setup and Hold Check definition and requirement (along with the Diagram).

In the above figure, Data "B" is divided into a range (from Bmin to Bmax). Now, you can easily visualize the condition of Setup and Hold Violation.

Setup Violation:

• If "Bmax" lies in the Gray area across Edge "3", it's consider a Setup Violation. OR
• I can say that if Data Range (Red area across data "B") overlap Gray area across Edge "3", it's a Setup Violation.
• It means for Setup Check, we consider "Maximum Data Path Delay" (In above example, it's "Bmax").

Hold Violation:

• If "Bmin" lies in the Red Brown area across Edge "2", it's consider a Hold Violation. OR
• I can say that if Data Range (Red area across data "B") overlap Red Brown area across Edge "2", it's a Hold Violation.
• It means for Hold Check, we consider "Minimum Data Path Delay" (In above example, it's "Bmin").

Now 1 interesting question - Is it possible that Bmin and Bmax will overlap Gray (across Clock Edge "3") and Red_Brown (across Clock Edge "2") area at the same time ? Yes It is... And if this Possible - what does it mean ???
Same path has Setup and Hold violation at the Same Time.

I think, I am able to successfully answer both questions which you have asked me in the end of Previous Article.

So for Doing the Setup and hold checks, you have to give a lot of inputs to the Timing Analysis tool and then it will do the calculation, figure out the min and max delay of the Data path and check whether there is any overlap or not with the Setup and Hold Window across The Clock Edge. If we miss any input, report provided by the Timing analysis tool will not be correct. That's the reason we do the Timing analysis several time during the whole design Cycle. As we move forward, we get more clarity about the inputs/condition, we feed those inputs to timing analysis tool and try to fix setup and hold violation incrementally.
Other flip side of this - It's not a easy job and Run time will be huge.

So the Question come - How can we reduce the complexity of the Inputs and also decrease the Analysis time. For this, different Timing tools have different methodology but a very common way is "Adding the Pessimism in the calculation of Delay Value". This helps even in providing less input (or say impose less conditions) to timing tool and it become fast.

I am not suppose to mention that:
After the Pessimism, Min value of Data path Delay < actual min_value of Data path Delay.
After the Pessimism, Max value of Data path Delay > actual max_value of Data path Delay.


If you are able to fix Setup and Hold Violation in this condition - means It's already ready for actual value. But problem comes when you are not able to fix with these Pessimistic values. Then we have to debug a lot (or say dig a lot) and has to figure out

• Whether these are real violations or not?
• If These are real violation, what's the root cause of that and what's the solution of that?

We will discuss in detail about these questions in next Article.