Layout Design Rules: Design Rule Check (DRC)

Index	Chapter1	Chapter2	Chapter3	Chapter4	Chapter5
	Digital Background	Semiconductor Background	CMOS Processing	CMOS Basic	CMOS Layout Design

5.1	5.2
Layout Design Introduction	Design Rule Check (DRC)

We already know that Layout is drawing version of the mask (mask which used in the manufacturing process). We should also know that Layout can’t be perfectly reproduced on the wafer. There are number of reasons and facts behind that. We will discuss all those separately. Most of the time Foundry knows about the gaps or the constraints of converting the Layout/Mask into the final manufacturable product. So they come up with set of rules which we all should comply. These rules are known as Design Rules.
Design rules ensure that design is still functional even when there may be lots of misalignments and various side-effects of the fabrication process.
In the CAD or say EDA (Electronic Design Automation) world, to verify these rules, different tools are developed by the EDA vendors, commonly known as DRC (Design Rule Checking or Checks) tools.

Let’s summarize some important points (theoretical part) before I will start more pictorial things. These points help you to understand different aspect of Layout Design Rule and Design Rule Checks (DRC).

• Design rules or say layout rules are defined as per the dimensions on wafer. When we draw these rules with the help of CAD tools, it looks to us that we are drawing really a very big diagram but actually if you will notice, there size “unit” is very small. So in short, all this has to be taken care by CAD tools.
• Design rules are written to verify shapes and sizes of various circuit components that are diffused in, deposited on, or etched on a semiconductor wafer.
• Foundry defines thousands of DRC rules in each Technology nodes. Complexity of these rules increases as you go down / lower the technology nodes.
• Different foundry defines these rules differently as per their manufacturing process constraints. There may be several rules which are not present in one foundry and present for other foundry for a same technology Node. But still there are few basics rules which are almost common to all foundry.
• Remember design rule checks do not validate that the design will operate correctly, they are constructed to verify that the structure meets the process constraints for a given design type and process technology.
• There is no standard in which language or way the Design rules should be written. Foundries provide the DRM (Design Rule Manual) in the form of pdf or word, where they document all the Rules.
• For the EDA tools, different vendors have different ways to code these rules in different format, so that their corresponding tools understand those rules and perform corresponding checks accordingly. A set of rules for a particular process is referred to as a run-set, rule deck, or just a deck.
• DRC is a very computationally intense task, It takes from few Hr to Few Days depends on the complexity of Design and the type of machine resources you are using.

EDA vendors and their Corresponding DRC tools.

• IC Validator and Hercules by Synopsys.
• Assura and PVS by Cadence Design System.
• Caliber by Mentor Graphics.

Now we are going to discuss few of the Layout Geometrical Terminology. Again, remember that different foundry has different Nomenclature for the same thing. But here, we are only specifying which are common across the industry (as per my best understanding).

Layout Terminology

Now let’s talk about few examples about the Design Rules. This will help you to understand more clearly from Layout/Design point of view.
Note: I haven’t write the dimensions of any rule because these can be changed as per the technology and as per the foundry.
Pictorial view of rules are next to them for more understanding closely.

Layer	Description	Label	Rule
Diffusion	Min Width	A	>=W.D
	Min Space	B	>=S.D
	Min Space between 2 DIFF1 with in DIFF2	C	>=S1.D
	Maximum DIFF length between 2 contacts	D	<=L.D
	DIFF must be fully covered by N/P select

Diffusion Related Rules

Layer	Description	Label	Rule
N-Well	Min Width	E	>=W.NW
	Min Space	F	>=S.NW
	Min Space to N+ Diffusion/Active	G	>=S1.NW
	Min Enclosure of P+ Diffusion / Active	H	<=E.NW
	Min Space to P Select	I	>=S2.NW
	Min Enclosure of N select	J	>=E1.NW

N-WELL Related Rules

Layer	Description	Label	Rule
Poly	Min Width	K	>=W.PC
	Min Space	L	>=S.PC
	Min Poly Extension On Diffusion	M	>=E.PC
	Min Diffusion Extension On Poly	N	<=E1.PC
	Min Space between Poly and Diffusion	O	>=S1.PC
	Poly over Diff must Divide Diff into at least 2  Diff regions

Poly Related Rules

Layer	Description	Label	Rule
Contact	Width (Minimum = Maximum)	P	=W.C
	Minimum Space	Q	>=S.C
	Min Space (When Contacts are on different Nets)	R	>=S1.C
	(Contact over Diff) minimum Space to Poly	S	>=S2.C
	(Contact over Poly)minimum Space to Diff	T	<=S3.C
	Enclosure by Diff	U	>=E.C
	Enclosure By Poly	V	>=E1.C

Contact Related Rules

Layer	Description	Label	Rule
Metal 1	Min Width	W	>=W.M
	Minimum Spacing	X	>=S.M
	Enclosure of Contact	Y	>=E.M
	Maximum Width	Z	<=W1.M

Metal 1 Related Rules

I am sure by now you have understood the Importance of Layout Design Rules. Now let me summarize this article with the CMOS inverter Layout (which we have drawn in last article) with the Layout Design Rules indication. You can yourself figure out that just for a small circuits we have to take care so many Design rules (Where above design rule list is just 1% of the actual design Rules), what will happen when we are going to design a complete chip.

Layout Design Rules in  a Simple "CMOS Inverter".

In the next article we will discuss few more layout of some complex circuits.

CMOS Layout Design: Introduction

CMOS Layout Design: Introduction

Index	Chapter1	Chapter2	Chapter3	Chapter4	Chapter5
	Digital Background	Semiconductor Background	CMOS Processing	CMOS Basic	CMOS Layout Design

5.1	5.2
Layout Design Introduction	Design Rule Check (DRC)

In the CMOS Processing series, we have learnt about the different fabrication steps in more detail with the help of diagrams. I have also mentioned that those were basically the side view of the fabrication process. I have also try to summarize each article with the help of 3D view. But in the world of CAD tools, designers talks about the TOP view, which is known as LAYOUT of the design. We will learn more about the layout in detail in the next few articles, but this article will help you to understand the CMOS layout based on fabrication steps which we have learn in the CMOS fabrication series.

In this article, I will summarize the TOP view along with the 3D and side view. I am sure it will help you to understand the layout of CMOS inverter.

Note: Before I will start the layout of CMOS, Just wanted to make one thing very clear that during the layout designing, sequence of different layers in a mask layout is completely arbitrary, it does not have to follow the actual fabrication sequence. Layout is drawing the masks used in the manufacturing process. So at the end of the day, Foundry is going to create different Mask on the basis of Layout which designer has prepared. So from Foundry side, it doesn’t matter in which sequence you have design the Layout/mask. For them it’s matter whether Mask is correct or not. How this Layout info transferred to Foundry and in which form – we will discuss all this later on.

I will use following layers during our discussion.

I am sure you have question about the N-select and P-select because we never discussed about these layers till now. What are there layers and what’s the use of these? Let me explain these first before we start anything.

Active and N/P Select layers:

Active layer in a layout defines openings in the silicon-di-oxide covering the substrate. N-select or P-select layers indicates where to implant n-type or P-type atoms respectively. The active and select layers are always used together.

Consider the below figure. Here we have took example of the Substrate as a BOX which has Field Oxide (FOX) on the top of that. You can see that the Active layer as a BOX which indicates where to open a hole in the field oxide. These openings are called Active Area. Rest of the Field area (which is not the active area) is used for the routing purpose.

MOSFETs are fabricated in these active areas or you can say these active openings (both PMOS and NMOS). Pwell or Nwell, if required are also inside these openings. This FOX is used to isolates the devices from one another or say active areas.

Surrounding the active layers with either the n-select or the p-select layers dopes the semiconductor n-type or p-type. Below diagram helps to understand the different combinations of active, p-select, n-select and N-well layers. You can think or visualize the different layers and their cross-sectional layer in the following way. Always remember – opening in the FOX is implanted by p-type / n-type if that location is determined by p-select mask / n-select mask.

You may be thinking that why n-select or p-select mask is greater than the Active mask/layer. Actually it depends on the alignment of the 2 masks. If p-select / n-select mask is properly aligned with the active layer mask then there is no need of any extra p-select around the Active layer. But to take precaution or avoiding any misalignment (which can stop to dope the active region with proper doping, either n type of p type), we keep the active layer mask smaller than the select layer mask.

Now let’s start comparing the different view of the CMOS inverter. Again – to understand the Side view, please go through the CMOS processing Series/Chapter.

Step 1: Draw N select, Nwell and P select layers.

Note: I haven’t draw the SiO2 layer here. Because this is our understanding that rest of the portion/area where no layer present, SiO2 is present.

Step 2: Draw Poly layer.

Note: This Poly in the layout is same for GATE Poly and FIELD POLY. In Few cases there are different layers are defined for these type of layers which helps CAD tool to recognize. In the lower technology (14nm, 10nm), sometime these two type of Poly layers also have different properties. Similarly, for PMOS and NMOS right now we are using same POLY layer but in lower technology (14nm, 10nm) these are also identify with different layer names. I will explain these things later on in some other article.

Step 3: Draw N+ Diffusion For NMOS. For PMOS Body Contact, Draw N-select, N+ diffusion.

Step 4: Draw P+ Diffusion for PMOS devices.

Step 5: Draw Metal Contact and Metal M1 which connect Contacts.

I think, now you can see that it’s far easy to draw a layout in comparison to the 3D view or Side view. But it’s far easy to understand in the 3D view and side view.

More familiar layout of CMOS inverter is below.

Note: We haven’t applied any design rules here or any type of layout design constraints. I just want to show you the differences in different view. We will discuss the design rules and layout design on the basis of design rules in next few articles in more detail.

Create Contact and Metal-M1: CMOS Processing (Part 6)

Create Contact and Metal-M1

Index	Chapter1	Chapter2	Chapter3	Chapter4
	Digital Background	Semiconductor Background	CMOS Processing

3.1	3.2	3.3	3.4	3.5	3.6
Fabrication Steps	Create N-Well and Field Oxide	Create Gate Oxide and Poly Layer	Implant N+ Impurities	Implant P+ Impurities	Create Metal Contact

Just to remind you that the complete CMOS fabrication process, we are not discussing in a single post. Complete CMOS fabrication, I have divided into different post as per above table.


Let’s start where we have left in the last post (3D view of the wafer).

Please follow the following steps, to create the Contact and the M1 Interconnects.

Final 3D View of silicon wafer.

Till Now we have created

• Nwell
• Active Region
• Channel Stop Region
• Field Oxide.
• Gate Oxide
• Poly layer.
• N+ regions (Source and Drain) for NMOS device.
• P+ regions (Source and Drain) for PMOS device.
• Metal Contact and Metal M1.

Below the Metal 1 fabrication, the Process is known as FEOL (Front-End-Of-Line) process. After the last FEOL step, there is a silicon wafer with isolated transistors (without any wires). In BEOL (Back-End-Of-Line) part of fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. Details of FEOL and BEOL – theory we will discuss in next few post.

Till now in all the above few post we have discussed the Side view of the MOSFET (CMOS) fabrication for better understanding for creating different geometries. But in real world, VLSI designer don’t use this view for designing purpose. We as a VLSI designer always use CAD tools for designing the MOSFET shapes and in the CAD tools we always talk about the TOP VIEW. In the next post we will summarize TOP view along with the Side View along with the process of creating the CMOS inverter with the help of CAD tools.

Implant P+ Impurities: CMOS Processing (Part 5)

Implant P+ Impurities: CMOS Processing (Part 5)

Index	Chapter1	Chapter2	Chapter3	Chapter4
	Digital Background	Semiconductor Background	CMOS Processing

3.1	3.2	3.3	3.4	3.5	3.6
Fabrication Steps	Create N-Well and Field Oxide	Create Gate Oxide and Poly Layer	Implant N+ Impurities	Implant P+ Impurities	Create Metal Contact

Just to remind you that the complete CMOS fabrication process, we are not discussing in a single post. Complete CMOS fabrication, I have divided into different Article as per above table.

Let’s start where we have left in the last post (3D view of the wafer).

Few things are important (Few points are just copy paste from the previous post for better understanding.:) )

• This is the ideal process. In actual fabrication the Gate Length is affected. I have explained that in the last post. Please refer that.
• We are going to add Boron as part of P+ impurities. We can add other also.
• As a part of side effect of this process, resistance of poly decreases, Pfet threshold affected. But we are not going to discuss all these in this post.
• NMOS needs a body contact (which will be of p+ doping) the same as the Source(GND)
• PMOS needs a body contact (which will be of n+ doping) the same as the Drain (Vdd)
• From process and steps point of view, there is no difference while creating the NMOS and PMOS devices (except mask and the impurities). So we can interchange the steps (Means First we can create PMOS and then NMOS).
• In this we are going to create PMOS (Source and Drain) only. We are not creating the NMOS body contact (just because of space issue in the diagram) but the concept remains same as in case of PMOS body contact as we have discussed in the previous post.

Final 3D view of the Silicon Wafer is:

Till now we have created

• Nwell
• Active Region
• Channel Stop Region
• Field Oxide.
• Gate Oxide
• Poly layer.
• N+ regions (Source and Drain) for NMOS device.
• P+ regions (Source and Drain) for PMOS device.

In the next post we will talk about adding Metal Contact which will help us to pass the signal or data to MOS devices from the other MOS devices or from the External world.

Implant N+ Impurities: CMOS Processing (Part 4)

Implant N+ Impurities:

Index	Chapter1	Chapter2	Chapter3	Chapter4
	Digital Background	Semiconductor Background	CMOS Processing

3.1	3.2	3.3	3.4	3.5	3.6
Fabrication Steps	Create N-Well and Field Oxide	Create Gate Oxide and Poly Layer	Implant N+ Impurities	Implant P+ Impurities	Create Metal Contact

Just to remind you that the complete CMOS fabrication process, we are not discussing in a single post. Complete CMOS fabrication, I have divided into different articles as per above table.

Let’s start with the 3D diagram of silicon wafer where we left in the last post.

Final 2 diagram of last post is little bit small in size for clarifying the further processing. So again I am just expanding that and start the process from there on. :)

Now we will start the process of implant of Phosphorus (N type impurities), to create an N+ region in the P-type substrate. Final outcome of this will be the NMOS devices.

Few things are important here.

• This is the ideal process. In actual fabrication the Gate Length is affected. I will explain with the diagram later in this post.
• We are going to add Phosphorus as part of N impurities. We can add other also.
• As a part of side effect of this process, resistance of poly decreases, Nfet threshold affected. But we are not going to discuss all these in this post.
• NMOS needs a body contact (which will be of p+ doping) the same as the Source(GND)
• PMOS needs a body contact (which will be of n+ doping) the same as the Drain (Vdd)
• From process and steps point of view, there is no difference while creating the NMOS and PMOS devices (except mask and the impurities). So we can interchange the steps (Means First we can create PMOS and then NMOS).

Note:

• In this post we will create the NMOS (Source and Drain) and PMOS body contact only.
• Next post will be related to PMOS (Source and Drain) only. We are not creating the NMOS body contact (just because of space issue in the diagram ) but the concept remains same.

As I have mentioned that the channel length will be different, please understand with the help of below diagram. Same concept is going to apply for channel length in case of PMOS devices (which we will not discuss there).

Now the 3D view of the final silicon wafer is:

Till now we have created

• Nwell
• Active Region
• Channel Stop Region
• Field Oxide.
• Gate Oxide
• Poly layer.
• N+ regions (Source and Drain) for NMOS device.

In the next post we will talk about adding P+ impurities which will help us to create PMOS devices.

Creating Gate Oxide and Poly Layer: CMOS Processing (Part3)

Creating Gate Oxide and Poly Layer

Index	Chapter1	Chapter2	Chapter3	Chapter4
	Digital Background	Semiconductor Background	CMOS Processing

3.1	3.2	3.3	3.4	3.5	3.6
Fabrication Steps	Create N-Well and Field Oxide	Create Gate Oxide and Poly Layer	Implant N+ Impurities	Implant P+ Impurities	Create Metal Contact

Just to remind you that the complete CMOS fabrication process, we are not discussing in a single post. Complete CMOS fabrication, I have divided into different Articles as per above table.

Let’s start with the 3D diagram of silicon wafer where we left in the last post.

 

 

In the last post we have talked about the Field Oxide and here is Gate oxide. The gate oxide is the dielectric layer (silicon Oxide) similar to the Field Oxide but very thin in size. It separates the gate terminal of a MOSFET from the underlying source and drain terminals.

 

 

 

Final 3D diagram of silicon wafer.

 

 

Now we will deposit the polysilicon layer which will act as GATE contact. This Polysilicon layer also known as POLY in short.

 

 

Note:

Poly layer above the gate oxide is also known as GATE POLY and the poly above the Field Oxide also known as FIELD POLY. In other word, you can say that POLY with in the active region is known as GATE POLY because it helps in forming the Gate of Device and POLY outside the active region is known as FIELD POLY.

Final 3D Diagram of Silicon Wafer :

 

Till now we have created

• Nwell
• Active Region
• Channel Stop Region
• Field Oxide.
• Gate Oxide
• Poly layer.

In the next post we will talk about adding N+ impurities which will help us to create NMOS devices.

 

Create N-well And Field Oxide: CMOS Processing (Part 2)

Create N-well And Field Oxide

Index	Chapter1	Chapter2	Chapter3	Chapter4
	Digital Background	Semiconductor Background	CMOS Processing

3.1	3.2	3.3	3.4	3.5	3.6
Fabrication Steps	Create N-Well and Field Oxide	Create Gate Oxide and Poly Layer	Implant N+ Impurities	Implant P+ Impurities	Create Metal Contact

If you think, I can explain the complete manufacturing steps in a single post then it’s not possible. So I will discuss this in a series of 4-5 post. Best part is – I will try to explain more with pictures and explain them in very short (in text). I will only discuss the concepts in between (if required). I have tried to make figures/diagram self explanatory. But still in case of confusion, feel free to ask me.

Complete CMOS fabrication, I have divided into different post based on below milestones.

• Create N-well and Field Oxide
• Creating Gate Oxide and Poly Layer
• Implant N+ Impurities
• Implant P+ Impurities
• Create Contact and Metal-M1

We want to fabricate a CMOS Inverter.

 

In the above diagram – you may have few questions and doubts. Let me add few points here which can help you.

• Only Photoresist is not sufficient to shield Silicon from Ion Implantation. So Oxide or Nitride is required to block the implant.
• There are 2 portion of Photoresist. Soluble/Soft portion (Portion on which UV rays falls) and Hard portion (Which is not exposed by UV)
• Solvent required to remove/dissolve the soft portion of photoresist is different from the solvent required to remove the hard portion.
• For CMOS process, both NMOS (N- Channel transistor) and PMOS (P-Channel transistor) are required. 
• For NMOS – P-type substrate is required
• For PMOS – N-type substrate is required.

We always talk about the P-type substrate and Not N-type Substrate. Question is why?
 

It’s not like P-Type substrate is available in the market and we are just using that. In the Market Silicon wafer is available and with the help of Doping – we convert that silicon wafer into P-type substrate. Now you will ask why we can’t convert this into N-type Substrate. And I will simple say – you can do that. No one is going to stop you. They why it’s not well known?
 

Actually – we can’t use 2 different substrate for design because in the design both PMOS and NMOS is present. We have to choose which is more beneficial from fabrication point of view. In general or say it’s true that NMOS devices are always more in the Semiconductor Industry in comparison to PMOS devices. For your reference-SRAM requires 6 transistors (4 NMOS, 2 PMOS)

Another reason for more number of NMOS is because of difference of mobility of electron and Holes. Electron mobility is almost twice of holes mobility and because of this ON-RESISTANCE of n-channel device is half of p-channel device with the same geometry and under the same operating conditions. That means to achieve same impedance size of n-channel transistors is almost half of p-channel devices. Same thing I can say in the different way that for same size of wafer, we can have more number of NMOS (means can perform more logical operation) in comparison to PMOS.

I hope above explanation helps you to understand the reason of well-known P-type Substrate. :) 

• For NMOS – we doped entire silicon wafer first with P-type impurities and make it P-type Substrate, where we can directly form N-channel devices.
• For PMOS – we have to separately create N Well selectively (by adding N-type Impurities in the selective regions).

Twin Tub (Twin-Well) CMOS Process:

There is a process where both type of Wells (N- Well and P Well) are present. Such process is known as Twin Tub (Twin-Well) CMOS process.

This process is required when we want to optimize different parameters independently (like threshold voltage, body effect and the channel transconductance). If we have p-type of substrate then all the NMOS can’t be optimized independently (because they have common P-type substrate). Similarly N-well is with in P-substrate, then there is some influence of this on PMOS also. I am not going to discuss all this right now. It’s just for your info. 

Device Isolation/Field Oxide (Channel Stop implants)

As I have mentioned above for better performance Devices should be electrically isolated from each other (both same type and different type of devices). Basically we want to suppress leakage current.

Best solution is to form a reverse bias pn-junction between 2 transistors. That means if we form positive doped region next to the negatively doped region (N-well next to P-well or vice versa), they can automatically form a reverse bias between 2 regions. Till the point there is a depletion layer between them, except reverse saturation current (very small leakage current) there will be no electrical connection between these 2 regions until voltage exceed breakdown voltage. To control the voltage between these 2 regions, we can tie n-region to most positive voltage (VDD) and p-region to most negative voltage (VSS).

Junction leakage current has dependency on the area of the depletion layer, so in case of large n and p region, this current will be significant and it will not solve the complete purpose.

In such cases, there is another general method – forming the dielectric layer between 2 transistors. This dielectric is very thick and known as Field Region (Field Oxide).

Few points about the Field Oxide

• Also known as Thick Oxide, Thick SiO2 insulator.
• Field Oxide is Thickest Oxide relative to other oxide layer present in the IC (e.g. Gate Oxide layer)
• This oxide region is different from the Gate oxide.
• The area where Field Dielectric is not present, is the area where Transistor exist. And this area is known as active region.
• There are 2 ways to form the Field Oxide Region (We will not discuss these 2 methods right now).
• LOCOS (LOCal Oxidation of Silicon).
• STI (Shallow Trench Isolation)

Field Oxide increases the transistor’s threshold voltage so that device always remains in Off-stage. This threshold voltage can be further increased by increasing the surface doping concentration, Called “Channel Stop” under the Field Oxide.

So the Isolation region are formed by 2 layers

• Channel Stop Implants/region (p+)
• Field Oxide layer

To increase the threshold voltage as much as possible, Channel shop region should be highly doped and Field Oxide layer should be as thick as possible.

Size of above final figure is small for clarifying the further processing. So now I am just expanding that and start the process from there on.

 

End results will be something similar to the below one (in 3D).

Till now we have created

• Nwell
• Active Region
• Channel Stop Region
• Field Oxide.

In the next post we will talk about Gate Oxide.

 

Fabrication Steps: CMOS Processing (Part 1)

Fabrication Steps: CMOS Processing

Index	Chapter1	Chapter2	Chapter3	Chapter4
	Digital Background	Semiconductor Background	CMOS Processing

3.1	3.2	3.3	3.4	3.5	3.6
Fabrication Steps	Create N-Well and Field Oxide	Create Gate Oxide and Poly Layer	Implant N+ Impurities	Implant P+ Impurities	Create Metal Contact

Property of material plays a very important role on the performance of MOSFET devices. If you are not agreeing with this statement, then maybe you have to refer device physic. But now just believe me. J

While we are fabricating the MOSFET, we have to take care about the different material used based on the performance of end product (MOSFET) and so we can say that properties of the material (which material, doping, sizes …) come from the Fabrication of the MOSFET. In this post, I am going to brief you about the different Fabrication steps of CMOS device and some important info which will help you to understand different terminology + fundamental of lower technology node process.

 

Just few basics:

Materials can be classified in to 3 main groups as per their electrical conducting property.

1. Insulator
• Used to isolate conducting or semiconducting material from each other.
• MOS devices and Capacitance require insulator for their physical operation.
• Which insulator is required – it depends on the functionality for which you want to use it.
• Few of the known insulators are
• Silicon Dioxide
• Silicon Nitride
2. Conductor
• Conductors are used in the IC world for electrical connectivity.
• These are used as Local interconnects, Global Interconnects and in Contact/VIAs.
• Few of the good conductors are:
• Silver
• Gold
• Copper
• Aluminum
• Platinum
3. Semiconductor
• This is the base of whole semiconductor Subject. Silicon is the known semiconductor material.
• This is very popular because of
• Physical characteristic
• Low cost because of easily available in the nature.
• Selective doping of various regions of silicon allows the conductivity of the silicon to be changed with the application of voltage.
• Other semiconductor material is GaAs but this use only for specific purpose/applications.

There are lot of processing technology are available in the market but only few are very popular. Out of which majority of production is done with Traditional CMOS. Others are limited to the area where CMOS is not very suitable (like High speed RF applications).

 

 

 

Few important concepts about the fabrication

• ICs are created on Silicon Wafer.
• Silicon Wafer is a very think disk of intrinsic Silicon on which rectangular or square shape of multiple ICs are created.
• Individual ICs are cut with the help of diamond saw and marked as pass or fail after proper testing.
• The individual IC is called a “die”

 

 

• On the basis of good no of die in a wafer, we define a term YIELD.

Yield = (No of Good die)/(Total No of die on the wafer)

• We always try to achieve 100% yield but that’s the ideal scenario. In a mature technology node or say process Yield approximately equal to 90%.
• Always remember – Yield decides the cost of the chip.
• All ICs on a same wafer are processed at the same time, so the time taken and process steps are same regardless the no of ICs in silicon wafer.
• This means the cost to process a wafer is the same whether it has 1 IC, or 1000 IC’s on it or not.
• Lower technology node process (e.g. 45nm) has more number of die in silicon wafer in comparison to higher technology node process (e.g. 180nm). 

 

 

Now we will understand few of the terminology which is linked with the Fabrication and now-a-days are more know to outside world. I will not discuss too much about these because we need not to know the every details (like equations, equipment in each process and all) of these steps. I will try to cover as much as possible which is required/ sufficient for CMOS fabrication point of view.

• Oxidation (Oxide Growth)
• Photolithography
• Etching
• Deposition
• Ion Implantation
• Annealing

Oxidation:

 

Note: In case you are interested in more details about this process, you can refer chapter 3 of VLSI Technology by S.M SZE.

Oxidation of Silicon is necessary throughout the IC fabrication process. SiO2 plays an important role in IC technology because no other semiconductor material has a native oxide which is able to achieve all the properties of SiO₂. Silicon Dioxide has several uses:

• To serve as a mask against implant or diffusion of dopant into the silicon
• To provide the surface passivation (creating protective SiO2 layer on the wafer surface). It protects the junction from moisture and other atmospheric contaminants.
• To isolate one dielectric from other.
• SiO2 acts as the active gate electrode in MOS device structure.
• Used to isolate one device from other.
• To provide the electrical isolation of multilevel metallization system.

Several techniques are there for forming oxide layer and each technique has their preferred uses.

1. Thermal Oxidation
1. When the interface between the oxide and the silicon requires a low charge density level, thermal oxidation has been preferred technique.
2. Vapor-Phase technique
1. Also know as Chemical Vapor Deposition (CVD)
2. When oxide layer is required on the top of a metal as in case of multilevel metallization structure, vapor-phase technique is preferred technique.

 

Just as a general principal and which you will see later – When Silicon exposed to oxygen – silicon dioxide form rapidly.  Remember – Silicon got consumed during this process.

There are 2 ways of doing oxidation. I can help you with the equations.

Si (Solid) + O₂ -> SiO­₂ (Solid)

• This process is known as Dry Oxidation.
• No byproduct.
• Form a thin layer of Silicon Dioxide.

Si (Solid) + 2HO₂ -> SiO­₂ (Solid) + 2H₂

• Know as Wet Oxidation.
• Hydrogen (H2) is the byproduct.
• Forms a thick layer of Silicon Dioxide.

Note:

• If heat is added to the process, the rate of SiO2 growth is sped up considerably
• This is called “Thermal Oxidation” which applies to both Wet and Dry processes
• Temperatures usually are in the range of 700 – 1300 C

Oxidation of Silicon surface:

 

Oxidation through a window in the oxides:

 

Selective Oxide Growth:

 

Note: above 3 diagrams are captured from CMOS Processing link.

 

Photolithography:

Note: In case you are interested in more details about this process, you can refer chapter 4 of VLSI Technology by S.M SZE.

A technique used in IC fabrication to transfer a desired pattern onto the surface of a silicon wafer. The word lithography comes from the Greek lithos, meaning stones, and graphia, meaning to write. It means quite literally writing on stones. In the case of semiconductor lithography (also called photolithography) our stones are silicon wafers and our patterns are written with a light sensitive polymer called a photoresist.

Few important points to know about photolithography:

• Process of lithography can be accomplished by selectively exposing parts of the wafer while other parts are protected.
• The exposed sections are susceptible to doping, removal, or metallization.
• Specific patterns can be created to form regions of conductors, insulators, or doping.
• Due to the large number of lithography steps needed in IC manufacturing, lithography typically accounts for about 30 percent of the cost of manufacturing.
• Designer do the following things:
• Drawing the “layer” patterns on a layout editor
• Silicon Foundry:
• Generate the Mask as per the layer pattern provided by Designer.
• Transfer the mask pattern to the wafer surface.
• Process the wafer to physical pattern each layer of the IC.

 

Lithography Process:

• Photoresist coating:
• A material that is acid-resistant under normal conditions.
• When exposed to UV light, the material becomes soluble to acids
• We put the photo resist on a wafer.
• There are 2 type of photo resist. Positive and Negative. Positive Photoresist is the most popular due to its ability to achieve higher resolution features

 

	Original State	After UV Exposure
“Positive Photoresist”	Insoluble	Soluble
“Negative Photoresist”	Soluble	Insoluble

• Exposure:
• Mask pattern is developed as per the design.
• A mask in an opaque plate (i.e., not transparent) with holes/shapes that allow UV light to pass
• The mask contains the pattern that we wish to form on the target wafer
• We pass the UV light and expose the photoresist region selectively as per the pattern present in the Mask.
• UV rays create a soluble pattern in the photoresist. Depending on the type of photoresist (negative or positive), the exposed or unexposed parts become resistant to certain types of solvents.
• Apart of UV light there are other type of exposing radiation are also present.
• Electron, X-rays or ions

• Development:
• Then we can soak the entire thing in acid/solvent and only the soluble photoresist (depends on positive or negative photoresist) is removed.
• The developed photoresist acts as a mask for patterning of underlying layers. We can also say that this allows us to form a protective barrier on certain parts of the wafer while exposing others parts.

Etching:

Just few points about etching. More in details you can refer my other post.

• Once the desired shape is patterned with photoresist, the etching process allows unprotected materials to be removed.
• Etches can remove Si, SiO₂, polysilicon, and metal depending on what we want to accomplish.

I was just reading an article and like below definition of this step. I hope you will also like it.

The Process which immediately follows the photolithography step is the removal of material from areas of the wafer unprotected by photoresist.

When I am going to discuss the different steps of CMOS fabrication in next few posts, you will get a very clear picture

Deposition:

Deposition is the process of laying down a thin film of material on the surface of a silicon wafer. During chip designing we use several such films. It is opposed of growing where it consumes part of the target / wafer (like Oxide Growth)

 

 

 

Note: Copied the above diagram from Internet.

 

Few important things about the deposition:

• These layers form wires and insulators that interconnect all the transistors of the device.
• Material examples are:
• SiO₂, nitride, poly, metal
• Materials are divided into 4 categories.
• Metal
• Aluminum alloys
• Tungsten
• Titanium Nitride
• Silicides
• Tungsten
• Molybdenum
• Titanium
• Polysilicon
• Dielectric
• Silicon Dioxide
• Silicon Nitride
• Phospho-silicate Glass
• Boro-phospho-silicate Glass

As per the process of Deposition it’s classified into 3 major areas

 

1. Chemical Vapor Deposition (CVD)
• This method are commonly used for depositing
• Polysilicon
• Dielectric
• Metals
• Silicides
• The films created by this method are uniform films with excellent step coverage.
• This method is very economical. Just chemical reaction is the limitation.
2. Physical Vapor Deposition (PVD)
• It involves the physical removal of material from a target via ion bombardment. This is similar to sand blasting.
• Film material flies away from the target and adheres to the wafer, making the desired film.
• It can be used to deposit any material on any substrate. Because it’s a physical in nature and doesn’t rely on a chemical reaction.
• This method is not as economical as CVD
• This method are commonly used for depositing
• Aluminum
• Gold and their alloys.
3. Epitaxy
• It’s a unique form of CVD. The purpose of epitaxial deposition is to grow additional single crystal silicon above the original wafer surface.
• It’s a very expensive method and only used in the MOS processing.
• Silicon
• MBE
• MOCVD

Ion Implantation:

• The process of adding impurities (B, P, As) to a silicon wafer. Adding impurities are also known as doping. (ni -> N_A, N_D).
• The Impurities means ions are accelerated toward the wafer with the help of Electric Field and it tunnel into the crystal structure.
• With the help of Lithography process, we can add these impurities selectively.

Annealing:

• When we add the impurities into the wafer then it breaks the covalent bond of the structure. To improve/fix this damage, Annealing is the process.
• Below figure helps you to understand.

  In the next part we will discuss about the various discuss different steps in the CMOS fabrication (Mostly only by Pictures).