We already know that Layout is drawing version of the mask (mask which used in the manufacturing process). We should also know that Layout can’t be perfectly reproduced on the wafer. There are number of reasons and facts behind that. We will discuss all those separately. Most of the time Foundry knows about the gaps or the constraints of converting the Layout/Mask into the final manufacturable product. So they come up with set of rules which we all should comply. These rules are known as Design Rules.
Design rules ensure that design is still functional even when there may be lots of misalignments and various side-effects of the fabrication process.
In the CAD or say EDA (Electronic Design Automation) world, to verify these rules, different tools are developed by the EDA vendors, commonly known as DRC (Design Rule Checking or Checks) tools.
Let’s summarize some important points (theoretical part) before I will start more pictorial things. These points help you to understand different aspect of Layout Design Rule and Design Rule Checks (DRC).
- Design rules or say layout rules are defined as per the dimensions on wafer. When we draw these rules with the help of CAD tools, it looks to us that we are drawing really a very big diagram but actually if you will notice, there size “unit” is very small. So in short, all this has to be taken care by CAD tools.
- Design rules are written to verify shapes and sizes of various circuit components that are diffused in, deposited on, or etched on a semiconductor wafer.
- Foundry defines thousands of DRC rules in each Technology nodes. Complexity of these rules increases as you go down / lower the technology nodes.
- Different foundry defines these rules differently as per their manufacturing process constraints. There may be several rules which are not present in one foundry and present for other foundry for a same technology Node. But still there are few basics rules which are almost common to all foundry.
- Remember design rule checks do not validate that the design will operate correctly, they are constructed to verify that the structure meets the process constraints for a given design type and process technology.
- There is no standard in which language or way the Design rules should be written. Foundries provide the DRM (Design Rule Manual) in the form of pdf or word, where they document all the Rules.
- For the EDA tools, different vendors have different ways to code these rules in different format, so that their corresponding tools understand those rules and perform corresponding checks accordingly. A set of rules for a particular process is referred to as a run-set, rule deck, or just a deck.
- DRC is a very computationally intense task, It takes from few Hr to Few Days depends on the complexity of Design and the type of machine resources you are using.
EDA vendors and their Corresponding DRC tools.
- IC Validator and Hercules by Synopsys.
- Assura and PVS by Cadence Design System.
- Caliber by Mentor Graphics.
Now we are going to discuss few of the Layout Geometrical Terminology. Again, remember that different foundry has different Nomenclature for the same thing. But here, we are only specifying which are common across the industry (as per my best understanding).
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| Layout Terminology |
Now let’s talk about few examples about the Design Rules. This will help you to understand more clearly from Layout/Design point of view.
Note: I haven’t write the dimensions of any rule because these can be changed as per the technology and as per the foundry.
Pictorial view of rules are next to them for more understanding closely.
| Layer | Description | Label | Rule |
| Diffusion | Min Width | A | >=W.D |
| Min Space | B | >=S.D |
| Min Space between 2 DIFF1 with in DIFF2 | C | >=S1.D |
| Maximum DIFF length between 2 contacts | D | <=L.D |
| DIFF must be fully covered by N/P select | | |
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| Diffusion Related Rules |
| Layer | Description | Label | Rule |
| N-Well | Min Width | E | >=W.NW |
| Min Space | F | >=S.NW |
| Min Space to N+ Diffusion/Active | G | >=S1.NW |
| Min Enclosure of P+ Diffusion / Active | H | <=E.NW |
| Min Space to P Select | I | >=S2.NW |
| Min Enclosure of N select | J | >=E1.NW |
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| N-WELL Related Rules |
| Layer | Description | Label | Rule |
| Poly | Min Width | K | >=W.PC |
| Min Space | L | >=S.PC |
Min Poly Extension On Diffusion
| M | >=E.PC |
| Min Diffusion Extension On Poly | N | <=E1.PC |
| Min Space between Poly and Diffusion | O | >=S1.PC |
| Poly over Diff must Divide Diff into at least 2 Diff regions | | |
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| Poly Related Rules |
| Layer | Description | Label | Rule |
| Contact | Width (Minimum = Maximum) | P | =W.C |
| Minimum Space | Q | >=S.C |
| Min Space (When Contacts are on different Nets) | R | >=S1.C |
| (Contact over Diff) minimum Space to Poly | S | >=S2.C |
| (Contact over Poly)minimum Space to Diff | T | <=S3.C |
| Enclosure by Diff | U | >=E.C |
| Enclosure By Poly | V | >=E1.C |
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| Contact Related Rules |
| Layer | Description | Label | Rule |
| Metal 1 | Min Width | W | >=W.M |
| Minimum Spacing | X | >=S.M |
| Enclosure of Contact | Y | >=E.M |
| Maximum Width | Z | <=W1.M |
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| Metal 1 Related Rules |
I am sure by now you have understood the Importance of Layout Design Rules. Now let me summarize this article with the CMOS inverter Layout (which we have drawn in last article) with the Layout Design Rules indication. You can yourself figure out that just for a small circuits we have to take care so many Design rules (Where above design rule list is just 1% of the actual design Rules), what will happen when we are going to design a complete chip.
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| Layout Design Rules in a Simple "CMOS Inverter". |
In the next article we will discuss few more layout of some complex circuits.
