Effect of Threshold voltage: Static Timing Analysis (STA) Basic (Part-7c)

STA & SI:: Chapter 2: Static Timing Analysis
2.1	2.2	2.3a	2.3b	2.3c	2.4a
Timing Paths	Time Borrowing	Basic Concept Of Setup-Hold	Basic Concept of Setup-Hold Violation	Examples:S-H Time/Violation	Timing Path Delay
2.4b	2.4c	2.5a	2.5b	2.6a	2.6b
Interconnect Delay Models	Delay - Wire Load Model	Maximum Clock Frequency	Calculate “Max Clock Freq”-Examples	Fix Setup-Hold Violation-1	Fix Setup-Hold Violation-2
2.6c	2.7a	2.7b	2.7c	2.8
Fix Setup-Hold Violation-3	Incr/Decr Delay Method-1	Incr/Decr Delay Method-2	Incr/Decr Delay Method-3	10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:

• Part1 -> Timing Paths
• Part2 -> Time Borrowing
• Part3a -> Basic Concept Of Setup and Hold
• Part3b -> Basic Concept of Setup and Hold Violation
• Part3c -> Practical Examples for Setup and Hold Time / Violation
• Part4a -> Delay - Timing Path Delay
• Part4b -> Delay - Interconnect Delay Models
• Part4c -> Delay - Wire Load Model
• Part5a -> Maximum Clock Frequency
• Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits.
• Part 6a -> How to solve Setup and Hold Violation (basic example)
• Part 6b -> Continue of  How to solve Setup and Hold Violation (Advance examples)
• Part 6c ->  Continue of  How to solve Setup and Hold Violation (more advance examples)
• Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew)
• Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew)
• Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew)
• Part 8 -> 10 ways to fix Setup and Hold Violation.

Effect of Threshold voltage on the propagation delay and transition delay:

 If you will see the below equations – I am sure you can easily figure out how threshold voltage effect the cell delay. (Note: Below Resistance formula is with respect to NMOS. You can derive similar formula for PMOS also (Just replace subscript “n” with “p” J ).

From above equation we have following points

• On Resistance of MOS is inversely proportional to the “V_DD-V_Tn” (where V_Tn is Threshold Voltage).
• Decreasing the threshold voltage (LOW V_Tn) increases “V_DD-V_Tn” for constant V_DD.
• Increasing “V_DD-V_Tn” means decreasing “On Resistance” R_n.
• Decreasing R_n à RC decreases.
• Means large Driving capability (Ability to source or sink current)
• Decrease the time to charge the output load (capacitance) (Consists of  source/drain capacitance of the driving gate, the routing capacitance of wire, and the gate capacitance of the driven gate) **
• Means “Output Transition time of Gate A” and “Input Transition time for Gate B” decreases.
• Decreasing the transition time means decreases the propagation time.

So we can say that…

"Delay can be reduced by using low Vt cells, but the cost paid is high leakage power"

Direct effect is that low Vt cells are often more leaky i.e. leakage power increases.

If still you have any confusion below diagram should clarify your doubts.

I hope above diagram should clear your doubts about the effect of Threshold voltage on Delay.

In the next post we will summarize/list down all the methods of fixing the setup and hold violations.