Effect of Wire Length On the Slew: Static Timing Analysis (STA) Basic (Part-7a)

(Effect of Wire Length On the Slew)

STA & SI:: Chapter 2: Static Timing Analysis
2.1	2.2	2.3a	2.3b	2.3c	2.4a
Timing Paths	Time Borrowing	Basic Concept Of Setup-Hold	Basic Concept of Setup-Hold Violation	Examples:S-H Time/Violation	Timing Path Delay
2.4b	2.4c	2.5a	2.5b	2.6a	2.6b
Interconnect Delay Models	Delay - Wire Load Model	Maximum Clock Frequency	Calculate “Max Clock Freq”-Examples	Fix Setup-Hold Violation-1	Fix Setup-Hold Violation-2
2.6c	2.7a	2.7b	2.7c	2.8
Fix Setup-Hold Violation-3	Incr/Decr Delay Method-1	Incr/Decr Delay Method-2	Incr/Decr Delay Method-3	10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:

• Part1 -> Timing Paths
• Part2 -> Time Borrowing
• Part3a -> Basic Concept Of Setup and Hold
• Part3b -> Basic Concept of Setup and Hold Violation
• Part3c -> Practical Examples for Setup and Hold Time / Violation
• Part4a -> Delay - Timing Path Delay
• Part4b -> Delay - Interconnect Delay Models
• Part4c -> Delay - Wire Load Model
• Part5a -> Maximum Clock Frequency
• Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits.
• Part 6a -> How to solve Setup and Hold Violation (basic example)
• Part 6b -> Continue of  How to solve Setup and Hold Violation (Advance examples)
• Part 6c ->  Continue of  How to solve Setup and Hold Violation (more advance examples)
• Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew)
• Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew)
• Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew)
• Part 8 -> 10 ways to fix Setup and Hold Violation.

Till now we have discussed the Ideal scenario for few of the cases. Like No Clock-to-Q delay, No Net Delay. But now we will discuss about those parameter also.

First understand/revise what are the different types or forms of Delay into a circuit.

In FFs:

• Clock to Q delay
• Propagation delay of sequential flip flop
• Time taken to charge and discharge the output load (capacitance) at Pin Q.
• Rise time and Fall time delay

Combinational Circuit:

• Cell delay
• Delay contributed by Gate itself.
• Typically defined as 50% input pin voltage to 50% output voltage.
• Usually a function of Both Output Loading and Input Transition time.
• Can be divide into propagation delay and transition delay.
• Propagation delay is the time from input transition to completion of a specific % (e.g 10%) of the output transition.
• Propagation delay is function of output loading and input transition time.
• Transition Delay is the time for an output pin to change the stage.
• Transition delay is function of capacitance at the output pin and can also be a function of input transition time.
• Time taken to charge and discharge the output load (capacitance) of the Cell output.

Net Delay:

• RC delay.
• Long wire has more delay in comparison to short wire.
• More coupling means more delay.

Now we will discuss different techniques to increase or decrease the delay in the design. We will also discuss the basics of different techniques, which will help us to understand why we are using any particular technique.

Now we have to see what best we can do to remove these violations or as explained earlier – How can we increase or decrease the delay of the clock or data path in the design. If I will ask you, then might be you can tell me 10 ways to do so. But I don’t want to explain in that way. Let’s start one by one with basics and then in the last I will brief all those points.

Let’s talk about the Transition delay first. There are 2 types of transition delays. Rise Delay and Fall delay. In terms of definition

• Rise Time Delay (tr):  The time required for a signal to transition from 10% of its maximum value to 90% of its maximum value.
• Fall Time Delay (tf):  The time required for a signal to transition from 90% of its maximum value to 10% of its maximum value.

Basically these times (rise time and fall time) are related to the Capacitance Charging and Discharging time.

So when capacitance is charging just because of any change in the input voltage then time taken by capacitance to reach from 10% to 90% of maximum value is known as rise time. Since this time (rise time) is going to introduce the delay in the circuit in comparison to the Ideal scenario (Capacitance charging time is Zero – It can charge instantly), it’s known as Rise Time Delay also.

Similarly, during the discharging of the capacitance from 90% to 10% of its maximum value, it’s going to add one more delay – known as Fall Time Delay.

Following figure is just an example of rise time and fall time. 

Note: Transition time is also known as Slew.

So we can say that Capacitance (and the associated Resistance) is the culprit. J And if we can play with capacitance/resistance, we can increase and decrease Transition Delay.

Now, whenever we are talking about any signal which is changing its state from “0” to “1” or from “1” to “0”, we are sure that it can’t be ideal (Ideal means its changing its state in Zero “0” time). If you have any doubt on this statement then defiantly I have to ask you to read some very basic books once again. J

Every “state changing signal” has a Slew Number (common name of Rise time and Fall time) associated with itself at any given point of time.

Effect of Wire length on the Slew (transition time):

In the below figure you can observe, how the step waveform (consider this as ideal one) degrades from the start to the end of the wire (color coding can help you to understand) and this is resulting a considerable amount of delay for long wires. That means if wire length is less, then degradation of waveform be less, means less effective delay and Vice-versa. We can conclude from this-

“If we want to increase the delay- we can increase the wire length and vice versa”

More simulation results you can see from this picture… (Following picture I have copied from book “DEEP SUBMICRON CMOS DESIGN” written by E.Sicard, S. Delmas-Bendhia )

I am sure you can cross question me that why this degradation is happing. Simple Ans is  - you can model a wire into a series of Resistance and Capacitance network. For more detail please refer following post Interconnect Delay Models.

Note: This delay is also known as Net delay/Wire Delay/Interconnect Delay.

In the next post we will discuss about the effect of Size of the Transistor on the "Transition Delay" and "Propagation Delay".