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Sunday, September 30, 2012

Maximum Clock Frequency : Static Timing Analysis (STA) basic (Part 5b)


STA & SI:: Chapter 2: Static Timing Analysis
2.1 2.2 2.3a 2.3b 2.3c 2.4a
Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay
2.4b 2.4c 2.5a 2.5b 2.6a 2.6b
Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2
2.6c 2.7a 2.7b 2.7c 2.8
Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:


Example 1: Multiple FF’s Sequential Circuit


In a typical sequential circuit design there are often millions of flip-flop to flip-flop paths that need to be considered in calculating the maximum clock frequency. This frequency must be determined by locating the longest path among all the flip-flop paths in the circuit. Consider the following circuit. 



There are three flip-flop to flip-flop paths (flop A to flop B, flop A to flop C, flop B to flop C). Using an approach similar to whatever I have explained in the last section, the delay along all three paths are:

  • TAB = tClk−Q(A) + ts(B) = 9 ns + 2 ns = 11 ns
  • TAC = tClk−Q(A) + tpd(Z) + ts(C) = 9 ns + 4 ns + 2 ns = 15 ns
  • TBC = tClk−Q(B) + tpd(Z) + ts(C) = 10 ns + 4 ns + 2 ns = 16 ns
Since the TBC is the largest of the path delays, the minimum clock period for the circuit is Tmin = 16ns and the maximum clock frequency is 1/Tmin = 62.5 MHz.

Example 2: Circuit with min and max delay Specification


Let’s consider following circuit. Now this circuit is similar to the normal FF circuitry, only differences are

  • Every specification has 2 values (Min and Max).
  • There is a combinational circuit in the clock path also.
Note: if you are wondering why there are min and max value (or like from where these values are coming, then you have to refer another blog).


Now let’s understand the flow/circuit once again.
  • Every interconnect wire also has some delay, so you can see clock CLK will take some time to reach the clock pin of the FF1.
  • That’s means with reference to original clock edge (let’s assume at 0ns), clock edge will take minimum 1ns and maximum 2ns to reach the clock pin of the FF1.
  • So in the similar fashion, if we will calculate the total minimum delay and maximum delay.
    • In data path : max delay = (2+11+2+9+2)ns=26ns
    • In data path : min delay = (1+9+1+6+1)ns=18ns
    • In clock path: max delay= (3+9+3)ns=15ns
    • In clock path : min delay = (2+5+2)ns=9ns
  • In the last 2 example, there were no delays in the clock path, so it was easy to figure out the minimum clock period. But in this example we have to consider the delay in the clock path also.
  • So for minimum clock period, we just want to make sure that at FF2, data should be present at least “tsetup” time before positive clock edge (if it’s a positive edged triggered flipflop) at the FF2.
    • So Clock edge can reach at the FF2 after 9ns/15ns (min/max) with the reference of original clock edge.
    • And data will take time 18ns/26ns (min/max) with the reference of original clock edge.
    • So clock period in all the 4 combinations are
      • Clock period (T1)= (Max data path delay)-(max clock path delay)+tsetup=26-15+4=15ns
      • Clock period (T2)= (Min data path delay)-(max clock path delay)+tsetup=18-15+4=7ns
      • Clock period (T3)= (Max data path delay)-(min clock path delay)+tsetup=26-9+4=21ns
      • Clock period (T4)= (Min data path delay)-(min clock path delay)+tsetup=18-9+4=11ns
  • Since we want that this circuit should work in the entire scenario (all combination of data and clock path delay), so we have to calculate the period on the basis of that.
    • Now if you will see all the above clock period, you can easily figure out that if the clock period is less than 21ns, then either one or all of the scenarios/cases/combinations fail.
    • So we can easily conclude that for working of the entire circuit properly
      • Minimum Clock Period = Clock period (T3) = (Max data path delay)-(min clock path delay)+tsetup=26-9+4=21ns
So in general:
Minimum Clock Period = (Max data path delay)-(min clock path delay) + tsetup

And "Maximum Clock Frequency = 1/(Min Clock Period)”

Example 3: Circuit with multiple Combinational paths between 2 FFs:





Now same scenario is with this example. I am not going to explain much in detail. Just it’s like that if you have multiple paths in between the 2-flipflops, then as we have done in previous examples, please calculate the delays.
Then calculate the time period and see which one is satisfying all the condition. Or directly I can say that we can calculate the Clock period on the bases of the delay of that path which has big number.
Min Clock Time Period = Tclk-q (of UFF1) + max(delay of Path1,delay of Path2) +Tsetup (of UFF3)


Example 4: Circuit with Different kind of Timing paths:




Since I have mentioned that it has different kind of timing path, so you should know about the timing paths. For that you can refer the (Post link) post. After reading the Timing path, you can easily figure out that in the above circuit there are 4 types of data paths and 2 clock paths

Data path:

  1. Register to register Path
    • U2 -> U3 ->U1 (Delay=5+8=13ns)
    • U1 -> U4 -> U2 ( Delay=5+7=12ns)
  2. Input pin/port to Register(flip-flop)
    • U7 ->  U4 -> U2 ( Delay=1+7=8ns)
    • U7 -> U3 -> U1 ( Delay=1+8=9ns)
  3. Input pin/port to Output pin/port
    • U7 -> U5 -> U6 (Delay=1+9+6=16ns)
  4. Register (flip-flop) to Output pin/port
    • U1 -> U5 -> U6 (Delay=5+9+6=20ns)
    • U2 -> U5 -> U6 (Delay=5+9+6=20ns)

Clock path:

  • U8 -> U1 (Delay = 2ns)
  • U8 -> U2 (Delay =2ns)

Now few important points- This is not a full chip circuit. In general, recommendation is that you use registers at every input and output port. But for the time being, we will discuss this circuit, considering this as full chip circuit. And you will how much analysis you have to do in this case. Next example, I will add the FFs (registers) at input and output port and then you come to know the difference.
Now let’s Study this circuit in more details.

  • In this circuit, we have to do the analysis in such a way that if we will apply an input at Port A, then how much time it will take to reach at output Port Y. It will help us to find out the time period of clock.
  • Output pin Y is connected with a 3input NAND gate. So if we want a stable out at Y, we have to make sure that all 3 Inputs of NAND gate should have stable data.
  • One input of NAND gate is connected with Input pin A with the help of U7.
    • Time take by data to reach NAND gate is 1ns (gate delay of U7)
  • Second input pin of NAND gate is connected with output pin Q of Flip flop U2.
    • Time take by data which is present at input D of FF –U2 to reach NAND gate:
      • 2ns(delay of U8)+5ns(Tc2q of FF U2)=7ns
  • Third input pin of NAND gate is connected with the output pin Q of Flip Flop U1.
    • Time take by data which is present at input D of FF –U2 to reach NAND gate:
      • 2ns(delay of U8)+5ns(Tc2q of FF U1)=7ns
Note:
  • I know you may have doubt that why delay of U8 comes in picture.
    • With reference to the clock edge at CLK pin, we can receive the data at NAND pin after 7ns only (Don’t ask me- why we can’t take reference in negative?)
  • May be you can ask why we haven’t consider the setup time of FF in this calculation.
    • If in place of NAND gate, any FF would there then we will consider the setup. We never consider the setup and Tc2q (Clk-2-Q) values of same FF in the delay calculation at the same time. Because when we are considering Clk-2-Q delay, we assume that Data is already present at input Pin D of the FF.

So Time required for the data to transfer from input (A) to output (Y) Pin is the maximum of:

Pin2Pin Delay = U7+U5+U6 = 1+9+6=16ns
Clk2Out (through U1) delay = U8 +U1+U5+U6=2+5+9+6=22ns
Clk2Out (through U2) delay = U8 +U2+U5+U6=2+5+9+6=22ns.
So out of this Clk2Out Delay is Maximum.

From the above Study, you can conclude that data can be stable after 7ns at the NAND gate and maximum delay is 22ns. And you can also assume that this much data is sufficient for calculating the Max Clock Frequency or Minimum Time Period. But that’s not the case. Still our analysis is half done in calculating the Max-clock-frequency.

As we have done in our previous example, we have to consider the path between 2 flip-flops also. So the paths are:
  • From U1 to U2 (Reg1Reg2)
    • Path delay= 2ns (Delay of U8) + 5ns (Tclk2Q of U1)+7ns (Delay of U4)+3ns (Setup of U2) – 2ns (Delay of U8)=17ns-2ns=15ns
  • From U2 to U1 (Reg2Reg1)
    • Path delay = 2ns (Delay of U8) + Tclk2Q of U2 (5ns) + Delay of U3 (8ns) + setup of U1 (3ns) – Delay of U8 (2ns) =18ns -2ns = 16ns.

Note:

  • I am sure you will ask why did I subtract “Delay of U8” from the above calculation :) because Delay of U8 is common to both the launch and capture path (In case you want to know what’s Launch and capture path please follow this post).  So we are not supposed to add this delay in our calculation. But just to make it clear, I have added as per the previous logic and then subtracted it to make it clear.

So now if you want to calculate the maximum clock frequency then you have to consider all the delay which we have discussed above.

So
Max Clock Freq = 1/ Max (Reg1Reg2, Reg2Reg1, Clk2Out_1, Clk2Out_2, Pin2Pin)
= 1/ Max (15, 16, 22, 22, 16)
=1/22 =45.5MHz



Example 5: Circuit with Different kind of Timing paths with Register at Input and output ports:


 


In this example, we have just added 2 FFs U8 at Input pin and U9 at output pin. Now for this circuit, if we want to calculate the max clock frequency then it’s similar to example 1.
There are 7 Flip flop to flipflop paths

  1. U8 -> U4 -> U2
    • Delay = 5ns+7ns+3ns=15ns
  2. U8 -> U3 -> U1
    • Delay = 5ns+8ns+3ns=16ns
  3. U8 -> U5 -> U9
    • Delay = 5ns+9ns+3ns=17ns
  4. U1 -> U4 -> U2
    • Delay = 5ns +7ns +3ns = 15ns
  5. U1 -> U5 -> U9
    • Delay= 5ns+9ns+3ns=17ns
  6. U2 -> U5 -> U9
    • Delay=5ns+9ns+3ns=17ns
  7. U2 -> U3 -> U1
    • Delay=5ns+8ns+3ns=16ns


Since the maximum path delay is 17ns,
The Minimum clock period for the circuit should be Tmin = 17 ns
And the Maximum clock frequency is 1/Tmin = 58.8 MHz.





Posted by VLSI Expert at 8:22 PM 86 comments

Monday, September 24, 2012

Maximum Clock Frequency : Static Timing Analysis (STA) basic (Part 5a)


STA & SI:: Chapter 2: Static Timing Analysis
2.1 2.2 2.3a 2.3b 2.3c 2.4a
Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay
2.4b 2.4c 2.5a 2.5b 2.6a 2.6b
Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2
2.6c 2.7a 2.7b 2.7c 2.8
Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:



This is a general question in most of the interview, what’s the maximum clock frequency for a particular circuit? Or Interviewer will provide some data and they will repeat the same question. Many of us know the direct formula and after applying that we can come across the final “Ans” but if someone twist the question. Some -time we become confuse. I motivation of this blog is the same. Several people asked me how to calculate the max-clock frequency. So I thought that it’s best if I can write something over this.

Here I will discuss the same but from basic point of view. It has 3 major sections.
  1. In 1st section, we will discuss different definitions with respect to Sequential and combinational Circuits.
  2. 2nd Section contains the basics of “Maximum Clock Frequency”. I will explain why and how you can calculate the max Clock frequency.
  3. I will take few examples and try to solve them. I will make sure that I can capture at least 2-4 examples from easy one to difficult one.

As we know that now a days all the chips has combinational + sequential circuit. So before we move forward, we should know the definition of “Propagation delay” in both types of circuits. Please read it once because it will help you to understand the “Maximum Clock Frequency” concepts.

Propagation Delay in the Combinational circuits:


Let’s consider a “NOT” gate and Input/output waveform as shown in the figure 


From the above figure, you can define
  • Rise Time (tr):  The time required for a signal to transition from 10% of its maximum value to 90% of its maximum value.
  • Fall Time (tf):  The time required for a signal to transition from 90% of its maximum value to 10% of its maximum value.
  • Propagation Delay (tpLH, tpHL):  The delay measured from the time the input is at 50% of its full swing value to the time the output reaches its 50% value.
I want to rephrase above mention definition as
  • This value indicates the amount of time needed to reflect a permanent change at an output, if there is any change in logic of input.
  • Combinational logic is guaranteed not to show any further output changes in response to an input change after tpLH or tpHL time units have passed.
So, when an input X change, the output Y is not going to change instantaneous. Inverter output is going to maintain its initial value for some time and then it’s going to change from its initial value. After the propagation delay (tpLH or tpHL - depends on what type of change- low to high or high to low), the inverter output is stable and is guaranteed not to change again until another input change ( here we are not considering any SI/noise effect).

Propagation Delay in the Sequential circuits:

 
In the sequential circuits, timing characteristics are with respect to the clock input. You can correlate it in this way that in the combinational circuit every timing characteristic/parameter are with respect to the data input change but in the sequential circuits the change In the “data input” is important but change in the clock value has higher precedence.  E.g in a positive-edged-triggered Flip-flop, the output value will change only after a presence of positive-edge of clock whether the input data has changed long time ago. 

So flip-flops only change value in response to a change in the clock value, timing parameters can be specified in relation to the rising (for positive edge-triggered) or falling (for negative-edge triggered) clock edge. 

Note: Setup and hold time we have discussed in detail in the following blogs. Setup and Hold part1; Setup and Hold part2; Setup and Hold part3 . But just to refresh your memories :) , I have captured the definition here along with “propagation delay”.

Let’s consider the positive-edge flip-flop as shown in figure.


Propagation delay, tpHL and tpLH , has the same meaning as in combinational circuit – beware propagation delays usually will not be equal for all input to output pairs. 

Note: In case of flip-flop there is only one propagation delay i.e tclk-Q (clock→Q delay) but in case of Latches there can be two propagation delays:  tClk-Q  (clock→Q delay)  and tD-Q (data→Q delay). Lation delay we will discuss later.
So again let me rephrase the above mention definition

  • This value indicates the amount of time needed for a permanent change at the flip-flop output (Q) with respect to a change in the flip flop-clock input (e.g. rising edge).
  • When the clock edge arrives, the D input value is transferred to output Q. After tClk−Q (here which is equivalent to tpLH), the output is guaranteed not to change value again until another clock edge trigger (e.g. rising edge) arrives and corresponding Input also.
Setup time (tsu) - This value indicates the amount of time before the clock edge that data input D must be stable.
Hold time (th) - This value indicates the amount of time after the clock edge that data input D must be held stable.
The circuit must be designed so that the D flip flop input signal arrives at least “tsu” time units before the clock edge and does not change until at least “th” time units after the clock edge. If either of these restrictions are violated for any of the flip-flops in the circuit, the circuit will not operate correctly. These restrictions limit the maximum clock frequency at which the circuit can operate (that’s what I am going to explain in the next section J )


The Maximum Clock Frequency for a circuit:


I hope you may be asking that why there is a need of explaining the combinational circuit propagation delay here. Combinational circuit is always independent of clock, so why combination circuit here. J
Now the point is combinational circuit plays a very important role in deciding the clock frequency of the circuit. Let’s first discuss an example and try to calculate the circuit frequency, and then we will discuss rest of the things in details. J
Note: Following diagram and numbers, I have copied from one of the pdf downloaded by me long time back. 




Now let’s understand the flow of data across these Flip-flops.

  • Let’s assume data is already present at input D of flip-flop A and it’s in the stable form.
  • Now Clock pin of FF (Flip-Flop) A i.e Clk has been triggered with a positive clock edge (Low to high) at time “0ns”.
  • As per the propagation delay of the sequential circuit (tclk-Q), it will take at least 10ns for a valid output data at the pin X.
    • Remember- If you will capture the output before 10ns, then no one can give you the guarantee for the accurate/valid value at the pint X.  
  • This data is going to transfer through the inverter F. Since the propagation delay of “F” is 5ns, it means, you can notice the valid output at the pin Y only after 10ns+5ns=15ns (with reference to the positive clock edge- 10ns of FF A and 5 ns of inverter)
    • Practically this is the place where a more complex combinational circuit are present between 2 FFs. So in a more complex design, if a single path is present between X and Y, then the total time taken by the data to travel from X to Y is equal to the sum of the propagation delay of all the combinational circuits/devices. (I will explain this in more detail in the next section with more example)
  • Now once valid data reaches at the pin Y, then this data supposed to capture by FF B at the next clock positive edge (in a single cycle circuit).
    • We generally try to design all the circuit in such a way that it operates in a single clock cycle. Multiple clock cycle circuit are special case and we are not going to discuss that right now (as someone says – it’s out of scope of this blog J )
  • For properly capturing the data at FF B, data should be present and stable 2ns (setup time) before the next clock edge as part of setup definition).
So it means between 2 consecutive positive clock edge, there should be minimum time difference of 10ns +5ns +2ns = 17ns. And we can say that for this circuit the minimum clock period should be 17ns (if we want to operate the circuit in single clock cycle and accurately).
Now we can generalize this
Minimum Clock Period = tclk-Q (A) + tpd (F) + ts (B)
And “Maximum Clock Frequency = 1/(Min Clock Period)”

Now at least we have some idea how to calculate the Max clock frequency or Min Clock Period. So even if we will forget the formula then we can calculate our self and we can also prove the logic behind that. Let me use the same concept in few of the more complex design circuit or you can say the practical circuit.




Posted by VLSI Expert at 2:31 PM 69 comments
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