Design constraint : Maximum (and minimum) Capacitance

7.4a	7.4b	7.4c
Maximum Transition Time	Maximum Fanout	Maximum And Minimum Capacitance

Design Constraints are divided into several parts because it’s really a wide and important topic. I want to discuss this in detail. I have also noticed that lot of information is present in internet but those are bits and pieces. So I am trying my best to cover everything here in a proper way. Let me know in case any of you have any feedback.

• Part 1a ->  Basics of Design Constraints and Details of "Maximum Transition Time" (max_transition) 
• Part 1b -> Maximum Fanout Constraint. (max_fanout)
• Part 1c ->  Maximum (and minimum) capacitance (max_capacitance and min_capacitance)
• Part 1d ->  Cell degradation (cell_degradation)

In the last part we have discuessed the max_fanout constraints and few details/basic of fanout in general also.

Note: Rest of the parts is still in development.

In the blog we will discuss regarding max_capacitance and min_capacitance constraints.

Maximum (and minimum) capacitance:

• The maximum (and minimum) total capacitive load that an output pin can drive. 
• The total capacitance comprises of load pin capacitance and interconnects capacitances. 
• This info is present in the .lib file. Please see the example with respect to one cell definition.
•  “max_capacitance” is available only for “output” pins.
•    Maximum Capacitance:
•  It is set as a pin-level attribute that defines the maximum total capacitive load that an output pin can drive. 
• That is, the pin cannot connect to a net that has a total capacitance (load pin capacitance and interconnect capacitance) greater than or equal to the maximum capacitance defined at the pin.
•  This definition of max capacitance is present in the .lib file as shown in example.
•  The max_capacitance value can vary with the operating frequency of a cell. (Because the capacitive load vary as per relationship of Xc=1/ωC .)
•   It may happen that you library is characterize for multiple frequency.
•  If that‘s the case then you can see one dimensional lookup table with max_capacitance value with each driver pin for each frequency in your .lib file.
•  Minimum Capacitance:
•  Some technology libraries specify minimum capacitance. 
•  The min_capacitance rule specifies the minimum load a cell can drive. It specifies the lower range of loads with which a cell has been characterized to operate.
• The load driven by a cell should meet the minimum capacitance requirement for that cell. If there is any violation then we can fix it by sizing the driver. 
• This is more of a modeling constraint and has lower priority in terms of being met.

Now you can also ask why there is need/significance/importance of this parameter?

Simple Ans is – if you have more output capacitance load then it will take more time to charge /discharge to/from  a particular logic level. It means more the delay of that cell is more. So whenever you are characterization libraries then you have to take care about all this parameters. More delay – means you can’t operate this cell for faster chip. More delay mean – there are more possibility of noise. And more important is More Power consumption (dynamic power consumption – we will discuss this in more detail in other blog).

Snapshot of *.lib file (Liberty File)

cell (<cellname>) {

cell_leakage_power : 3.748077e-03;

threshold_voltage_group : "si38p" ;

    area : "8.775" ;

    ….

    abc_cell () {

      …

      pin (Z) {

        direction : "output";

        }

      pin (CP) {

        direction : "input";

      }

      pin (D) {

        direction : "input";

      }

      ….

    }

pin (Z) {

      direction : "output";

      related_bias_pin : "VDDB VSSB";

      max_capacitance : 0.334971 ;

     max_fanout : 20 ;

      …

     timing () {
        cell_degradation (constraint) {
            index_1 ("1.0, 1.5, 2.0") ;
            values ("1.0, 1.5, 2.0") ;
        }

}

pin (CP) {

      clock : true;

      direction : "input";

      related_bias_pin : "VDDB VSSB";

      rise_capacitance : 0.001733;

      rise_capacitance_range(0.001268,0.002017);

      capacitance : 0.001706;

      fall_capacitance : 0.001680;

      fall_capacitance_range(0.001293,0.001938);

      max_transition : 0.550;

      …..

      }

}

In the next blog we will discuss about the Cell degradation.