"Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b)

STA & SI:: Chapter 2: Static Timing Analysis
2.1	2.2	2.3a	2.3b	2.3c	2.4a
Timing Paths	Time Borrowing	Basic Concept Of Setup-Hold	Basic Concept of Setup-Hold Violation	Examples:S-H Time/Violation	Timing Path Delay
2.4b	2.4c	2.5a	2.5b	2.6a	2.6b
Interconnect Delay Models	Delay - Wire Load Model	Maximum Clock Frequency	Calculate “Max Clock Freq”-Examples	Fix Setup-Hold Violation-1	Fix Setup-Hold Violation-2
2.6c	2.7a	2.7b	2.7c	2.8
Fix Setup-Hold Violation-3	Incr/Decr Delay Method-1	Incr/Decr Delay Method-2	Incr/Decr Delay Method-3	10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:

• Part1 -> Timing Paths
• Part2 -> Time Borrowing
• Part3a -> Basic Concept Of Setup and Hold
• Part3b -> Basic Concept of Setup and Hold Violation
• Part3c -> Practical Examples for Setup and Hold Time / Violation
• Part4a -> Delay - Timing Path Delay
• Part4b -> Delay - Interconnect Delay Models
• Part4c -> Delay - Wire Load Model
• Part5a -> Maximum Clock Frequency
• Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits.
• Part 6a -> How to solve Setup and Hold Violation (basic example)
• Part 6b -> Continue of  How to solve Setup and Hold Violation (Advance examples)
• Part 6c ->  Continue of  How to solve Setup and Hold Violation (more advance examples)
• Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew)
• Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew)
• Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew)
• Part 8 -> 10 ways to fix Setup and Hold Violation.

 Here we will discuss how to calculate the Setup and Hold Violation for a design.

Till now we have discussed setup and hold violation with respect to the single flipflop, now lets extend this to 2 flip flop. In the following fig there are 2 flipflops (FF1 and FF2).



Single-Cycle Setup and Hold For Flip-Flops



Few important things to note down here-

• Data is launching from FF1/D to FF1/Q at the positive clock edge at FF1/C.
• At FF2/D , input data is coming from FF1/Q through a combinational logic.
• Data is capturing at FF2/D, at the positive clock edge at FF2/C.
• So I can say that Launching Flip-Flop is FF1 and Capturing Flip-Flop is FF2.
• So Data path is FF1/C --> FF1/Q --> FF2/D
• For a single cycle circuit- Signal has to be propagate through Data path in one clock cycle. Means if data is launched at time=0ns from FF1 then it should be captured at time=10ns by FF2.

So for Setup analysis at FF2, Data should be stable "Ts" time before the positive edge at FF2/C. Where "Ts" is the Setup time of FF2.

• If Ts=0ns, then , data launched from FF1 at time=0ns should arrive at D of FF2 before or at time=10ns. If data takes too long ( greater then 10ns) to arrive (means it is not stable before clock edge at FF2) , it is reported as Setup Violation.
• If Ts=1ns, then, data launched from FF1 at time=0ns should arrive at D of FF2 before or at time=(10ns-1ns)=9ns. If data takes too long (greater then 9ns) to arrive (means it is not stable before 1ns of clock edge at FF2), it is reported as Setup Violation.

For Hold Analysis at FF2, Data should be stable "Th" time after the positive edge at FF2/C. Where "Th" is the Hold time of FF2. Means there should not be any change in the Input data at FF2/D between positive edge of clock at FF2 at Time=10ns and Time=10ns+Th.

• To satisfy the Hold Condition at FF2 for the Data launched by FF1 at 0ns, the data launched by FF1 at 10ns should not reach at FF2/D before 10ns+Th time.
• If Th=0.5ns, then we can say that the data launched from FF1 at time 10ns does not get propagated so soon that it reaches at FF2 before time (10+0.5)=10.5ns ( Or say it should reach from FF1 to FF2 with in 0.5ns). If data arrive so soon (means with in 0.5ns from FF1 to FF2, data can't be stable at FF2 for time=0.5ns after the clock edge at FF2), its reported Hold violation.

With the above explanation I can say 2 important points:

1. Setup is checked at next clock edge.
2. Hold is checked at same clock edge.

Setup Check timing can be more clear for the above Flip-flop combination with the help of following explanation.

Setup Check Timing

In the above fig you can see that the data launched by FF1/D ( at launch edge) reaches at FF2/D after a specific delay ( CLK-to-Q delay + Conminational Logic Delay) well before the setup time requirement of Flip-Flop FF2, so there is no setup violation.

From the Fig its clear that if Slack= Required Time - Arrival time < 0 (-ive) , then there is a Setup violation at FF2.

Hold Check timing can be more clear with the help of following circuit and explanation.





Hold Check Timing



 In the above fig you can see that there is a delay in the CLK and CLKB because of the delay introduced by the series of buffer in the clock path. Now Flip-flop FF2 has a hold requirement and as per that data should be constant after the capture edge of CLKB at Flip-flop FF2.
You can see that desired data which suppose to capture by CLKB at FF2.D should be at Zero (0) logic state and be constant long enough after the CLKB capture edge to meet hold requirement but because of very short logic delay between FF1/Q and FF1/D, the change in the FF1/Q propagates very soon. As a result of that there occurs a Hold violation.

This type of violation (Hold Violation) can be fixed by shortening the delay in the clock line or by increasing the delay in the data path.

Setup and Hold violation calculation for the single clock cycle path is very easy to understand. But the complexity increases in case of multi-cycle path ,Gated clock, Flip-flop using different clocks, Latches in place of Flip-Flop. We will discuss all these later sometime.