Process Variation - Effects On Design, Different Types and Modelling

The Scaling down of Process technologies has increased the Process variations. Because of this delay variation increases and impact the frequency performance of the design. These things also impacted the TAT (Turn Around Time) and timing yields (The ration of chips that achieve the target Frequency).

As a design specification its important to Target a particular frequency and Yield. Means how many chip can perform with in the target frequency after fabrication). Designer have done a lot of things to achieve this and one of the way is "adding sufficient margin" for delay variation.

In Process node above 90nm , the margins for the delay variations are small enough and their impact on the design can be eliminated but below 90nm increased Delay variation (because of Process variation) enlarge the margins in the circuit design. Because of this we have to overestimate delay in the design and which makes design work difficult (Increased the TAT of the design).

So its very important to understand that what are the delay variations?

Delay Variations are due to various type of process variations.

Type Of Process variation:

• Random Variation
• Occurs without regards to the location and patterns of the transistors with in the chip.
• E.g
• variation in transistor threshold voltage caused by density variations of impurities in the transistor material.
• Systematic variation
• Related to the location and patterns
• E.g
• Exposure pattern variation that occurred in lithography process.
• silicon surface flatness variations caused by layout pattern density variation during the CMP (Chemical Mechanical Planarization)
• Intra-die Or Within-die variation
• Variations between the elements in the same chip
• Inter-die Or Die-to-die variation.
• Variations between chips in the same wafer or in different wafers.

Part(a) is a type of  Random variation. Part(b) for Systematic variation and Part(c) for Die-to-die and within-die variations.

  

There are few more classification for the Process variations

• Front-end Variation
• Mainly refer to the variations present at the transistor level.
• The primary components of the front end variations
• transistor gate length
• gate width,
• gate oxide thickness,
• doping related variations. 
•  These physical variations cause changes in the electrical characteristics of the transistors which eventually lead to the variability in the circuit performance
• Back-end Variation.
• Refer to the variations on various levels of interconnecting metal and dielectric layers used to connect numerous devices to form the required logic gates

Now at least we have a rough idea about the type of Variations. Now next question is what is the solution of these variations. If these variations are there then how can we take care about this. So regarding this Foundries and EDA companies had done a lot of experiments and they always come with better solutions. 

One best way is To MODEL these variation (mathematically) and implement it during the designing cycle.

Lets Talk about these one by one.

Systematic Variation's Modeling:

• Controlled not like Random variation modeling where every thing is distributed.
• Generally Geometry-dependent or layout-dependent.
• Modeling is based on practical models. These models are implemented mathematically using different Tables(matrix), equations and simulators.
• Few of the area/causes on the basis of which modeling methods are decided
• ETCH modelling.
• Conductor's Width and Spacing Dependent ETCH.
• Device Specific
• Conductor Thickness variation.
• Density dependent
• Width and spacing dependent.
• Dielectric coefficient dependent.
• Dielectric thickness variation.
• Trapezoidal Line Shape and width enlargement (Trap tangent modelling)
• Damage Modelling.
• The intra-die variations, or variations within the same chip, are modeled using a deterministic process and are well controlled.

Random Variation's Modelling.

• Distributed , across different dies or even wafers
• Random and independent in nature.
• Manimum and minimun variation for a given parameter is usually know, along with the type of distribution the parameter exhibits. Usually this information is provided by the foundry.
• Commonly, we use "Normal Gaussian Distribution" based on "Central Limit Theorem" for modelling random variation.
• Based on Probability of occurance of a particular variation.
• Assumption: Variation of a paramenter is independent of rest of the factors and none of them playing dominant role.
• Random variations are modelled through process corners, where max and min variations represented by +3sigma and -3sigma.
• Following parameters are modelled as Random variations
• Thickness of
• Conductor
• Dielectric
• Width of Conductor.
• Dielectric Constant.
• Inter-die variations, or the process variation from die to die or wafer to wafer, are assumed to be random, and therefore are generally modeled using a normal and/or uniform distribution.

NOTE: There are lots of systematic variation, which are part of Random variation for lower technology node. Because as the chip size is decreases, Its very difficult to come-up a well defined equations/tables for few of the parameters. e.g thickness variation due to chemical mechanical polishing (CMP) or line width variation because of optical inaccuracies.

Note: Please refer the Corresponding Blog for the detail of specific variation/model types.