ETM (Extracted Timing Models) - More detail

6.1	6.2
ETM basics	ETM Advance

Lets Talk about ETM models little more: Check the ETM(Extracted Timing Models)-Basic blog for basic idea.

Advantage of Extracted Timing models:

• Much smaller than the original netlist.
• significantly reduce the time needed to analyze a large design.
• Using a model in place of a netlist prevents a user from seeing the contents of the block.

Extraction Requirement:

To generate these models you should have 

• Block netlist.
• Technology Library
• Timing details of the block.

As I have mentioned previously in one of my blog that Extracted timing models creates a timing arc for each path (port to port or port to register or register to port) in the original design (block). As we know that delay  in a design is accurate for a range of operating condition , but in the ETM models delay data does not depend on any specific parameter's value (like input transition times, output capacitive loads, input arrival times, output required times etc) and that's the reason these models are know as "context independent" models(condition applied ## [:)]). But when you are using these models in your design for timing analysis, then delay value depends on these parameters. So in other word I can say that these models are functions of different parameters and not limited to a specific set of parameter's values.

Timing information of different parts of the design in the Extracted models:

Nets:

• Boundary nets: Preserves the boundary nets of the design. Since these are the nets which will interact with the outside world (when you are going to instantiate this in the other design), so proper/correct and original  information is necessary to avoid any  mismatching.
• Internal Nets: Delay values are extracted in the models as per the information provided during the extraction. Means if you provide the "wire load models" then it will contain the information as per that or if you will provide detailed parasitics (of these internal nets), it will contain that information.

Paths:

• Input to register: Extracted into equivalent setup arc and hold arc between these 2. 
• Setup arc = delay of the longest path + setup time of the register library cell.
• Hold arc = delay of the shortest path + hold times of the register library cell.
• Note: 
• calculation between the shortest and longest path is between a particular input to all registers clocked by the same clock
• These values are function of transition time of input signal and clock, so if you are using this block in some other clock frequency (different then the value you have used during generation of these models), then you can do it easily.
• Register to Input: Same as above.
• Input to output path: Extracted into 2 equivalent arc (one is for shortest path and other for longest path).
• Register to register: Not extracted
• Clock path: Delays and transition times of clock networks are reflected in the extracted model.

Noise Analysis using These models: 

By default these is no noise information is included in extracted models. If you want then you can use special command for including noise characteristics in the extracted models.

Other Information:

There are lot of other information present in the extracted timing models. For that you can refer PrimeTime User Guide.

## "Context independent" doesn't mean that you can operate these models for any set of conditions. Before a timing model is created, the internal logic of the block is checked for timing violations, subject to external conditions such as input delay and output delay. Once verified, the internal timing of the model is guaranteed to have no violations as long as the external conditions are within the ranges specified when the internal logic was checked.

## SO before using these blocks you should know the range of these blocks (know as scope of the block). You can generate the scope file containing all these information also and check that one before using this in your design.

## Information stored in the ETM is in the form of delay table (A 2x2 Matrix). These matrix specifies the arc delay value as a function of the input transition time and the output load capacitance. Interpolation and extrapolation are performed for calculating the values other then specified in the table. These models are accurate for the range of values specified in the table.