ETM (Extracted Timing Models) basics

6.1	6.2
ETM basics	ETM Advance

Introduction:
In a design Once a block has met its timing constraints at the gate level, the detailed internal timing of the block is not needed for chip-level timing analysis. For that we can create/write a timing model for that block.

Timing Model of  the block

• Should completely model the full input/output timing characteristics without requiring the complete netlist of the block.
• Do not model every path in the block. Internal registerto register paths are generally discarded, as these paths can be analyzed at the block level using the complete gate-level netlist.

Synopsys has a tool named as PrimeTime and its most trusted and advanced timing sign-off solution for gate-level STA tool. Its accuracy is within 5% of SPICE.

Prime Time Provides following types of advance timing models.

• Interface Logic Models (ILM) for hierarchical static timing analysis and sign-off
• Extracted Timing Models (ETM) in .lib format for cell-based reusable IP and physical design flows
• Quick Timing Models (QTM) for top-down design

In this Blog we will discuss only about the ETM models basic. For More detail please refer "ETM (Extracted Timing Models) - More detail" blog.

ETM (Extracted Timing Models):-

• Block based model (.lib)
• Contents of block are hidden
• Original netlist replaced by model containing timing arcs for block interfaces.
• NLDM lookup tables are extracted for each of the timing arcs.
• These arcs whose delay are a function of input transition and output load. This makes ETM usable with different input transition times and different output loads.
• Multiple modes per model
• Single PVT per model
• Used for implementation (not sign-off) of IP models. Here the content are protected because the model contains abstracted timing information, without any netlist information.

ETM model Illustration:

Types Of ETMs:

There are 2 types of ETM avaliable-

• NetList
• Liberty library cell (.lib)

Note: Most frequent usages is the .lib cells. 

Developing of ETM Models:

Developing an ETM model in Primetime consists of three high level steps:

• Preparing for the ETM
• Creation of the ETM
• Verification of the ETM

ETM scripts example:

As such the flow of the script vary from design to design and company to company, but following example just give a rough idea about the commands for generating the ETM. I will suggest you to check the PrimeTime user-guide for more details.

• ETM creation :

############################################

# Template for ETM extract when using spef #
############################################
 
set BLOCK "blockname"
set NETLIST "blockname.v"
set SPEF "blockname.spef"
set SDC "blockname.sdc"
 
# Preserve unconnected nets
set svr_keep_unconnected_nets true
 
# set search_path and link_library
 
# Read and link netlist
read_verilog $NETLIST
current_design ${BLOCK}
link
#  for nets not annotated
set_wire_load_model -name B0.1X0.1
# Read spef
read_parasitics $SPEF
# Read constraints
read_sdc $SDC
set_propagated_clock [all_clocks]
 
 
# Define operating conditions
set_operating_conditions -library g65xp lsiW_090V_125C \
  -analysis_type on_chip_variation 
 
# Set extract_model variables
# Note: These should be considered example settings. Final variable
# settings ultimately depend on the specific design usage.
set extract_model_data_transition_limit 0.75
set extract_model_clock_transition_limit 0.75
set extract_model_capacitance_limit 1.0
set extract_model_num_clock_transition_points 7
set extract_model_num_data_transition_points 7
set extract_model_num_capacitance_points 7
set extract_model_use_conservative_current_slew true
set extract_model_enable_report_delay_calculation true
 
# to create an ETM model with propagated clocks:
set extract_model_with_clock_latency_arcs true
extract_model -output ${BLOCK} -format {db lib} \
 -library_cell -test_design
 
quit

############################################

ETM verification:    

############################################
# Template for ETM verification            #
############################################
 
set BLOCK "blockname"
set NETLIST "blockname.v"
set SDC "blockname.sdc"
set ETM_MODEL "${BLOCK}_lib.db"
set ETM_TEST  "${BLOCK}_test.db"
set ETM_CONST "${BLOCK}_constr.pt"
 
# Compute the interface timing of the netlist.
 
# Read in reference netlist design
read_verilog $NETLIST
current_design ${BLOCK}
link
set_wire_load_model -name B0.1X0.1
read_parasitics $SPEF
read_sdc ${SDC}
set_propagated_clock [all_clocks]
set_operating_conditions -library g65xp lsiW_090V_125C \
  -analysis_type on_chip_variation
write_interface_timing netlist_report.txt
 
 
# Compute the interface timing of the ETM model.
 
# Remove reference netlist and read in ETM model
remove_design -all
lappend link_path ${ETM_MODEL}
read_db ${ETM_TEST}
current_design ${BLOCK}_test
link
# set wire_load that has 0.0 cap loading
set_wire_load_model -name TSMC_CLN90G_WLM_0.0
## alternatively, use
#set_load -wire_load 0 *
read_sdc ${SDC}
set_propagated_clock [all_clocks]
source ${ETM_CONST}
write_interface_timing model_report.txt
 
# Compare the interface timing for the netlist vs ETM model.
 
compare_interface_timing -absolute_tolerance 0.1 \
 netlist_report.txt model_report.txt -output cmp.rpt
 
quit

#######################################################