STA & SI

Chapter 1: Introduction

• 1.1a Timing Arc
• 1.1b Unate: Timing Arc
• 1.1c Unateness of Complex Circuit: Timing Arc
• 1.2a LIB File syntax of Unateness of Logic Gates: Timing Sense
• 1.2b LIB File syntax of Unateness of Complex Combinational Circuit: Timing Sense
• 1.2c LIB File Syntax for Sequential Circuit

Chapter 2: Static Timing Analysis

• 2.1Timing Paths
• 2.2Time Borrowing
• 2.3.a Basic Concept Of Setup and Hold
• 2.3.b Basic Concept of Setup and Hold Violation
• 2.3.c Practical Examples for Setup and Hold Time / Violation
• 2.4.a Delay - Timing Path Delay
• 2.4.b Delay -Interconnect Delay Models
• 2.4.c Delay - Wire Load Model
• 2.5.a Maximum Clock Frequency
• 2.5.b Examples to calculate the “Maximum Clock Frequency” for different circuits
• 2.6.a How to solve Setup and Hold Violation (basic example)
• 2.6.b Continue of... How to solve Setup and Hold Violation (Advance examples)
• 2.6.c Continue of...How to solve Setup and Hold Violation (more advance examples)
• 2.7.a Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew)
• 2.7.b Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew)
• 2.7.c Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew)
• 2.8 10 ways to fix Setup and Hold Violation.

Chapter 3: Clock

• 3.1 Sources Of Clock Skew
• 3.2 Types Of Clock Skew

Chapter 4: Advance Static Timing Analysis

• 4.1 Setup And Hold Checks
• 4.2 Setup And Hold Violation
• 4.3a Path Base Analysis Vs Graph Base Analysis (Part 1)
  

Chapter 5: Signal Integrity

• 5.1 Introduction

Chapter 6: STA using EDA Tool

• 6.1 Static Timing Analysis Using EDA Tool
• 6.2 Static Timing Analysis Using EDA Tool .. (...continue)

Chapter 7: Timing Models

• 7.1.a ETM (Extracted Timing Models) Basics
• 7.1.b ETM (...continue)

Chapter 8: Other topics (Will categorize later)

• 8.1.a How To read SDF (Standard Delay Format)
• 8.1.b How To read SDF (...continue)
• 8.1.c Standard Delay Format (...continue)
• 8.2 CRP (Clock Reconvergence Pessimism)
• 8.3 Synopsys Design Constraints (SDC)
• 8.4a Design Constraint: Maximum Transition Time
• 8.4b Design Constraint: Maximum Fanout
• 8.4c Design Constraint: Maximum and Minimum Capacitance